Another motivation would be getting rid of software complications inherent to hybrid designs. (page 1)

I mean Intel is still rumored to continue having hybrid client CPUs post unified core too. So it does not sound like that is happening.

Lion Cove's L2 cache and the attached bus interface take up just over 40% of core area, making the L2 the largest block by far. However, Lion Cove needs the large L2 because Intel's uncore has poor latency characteristics. (page 2)

Also why I think core area discussions have to be more nuanced than just looking at the core + L2. Is it really the core's fault that Intel's uncore has been so poor for generations now? The uncore being so slow and high latency doesn't even seem to be any sort of 'PPA' trade off, it just seems like Intel can not get a fast L3 in client or in DC. I don't think their L3 iso process is particularly dense either? I haven't checked so I could be wrong on that.

M4's P-Core occupies a tiny bit more area than trimmed Zen 5, which also makes it larger than Lion Cove. (page 2)

Also helps explain how Apple's P-cores are so performant. Their cluster area savings come from the fact that they use a shared L2 cache with no L3, not because the logic in their cores are small.

Lion Cove may not suffer the area problems that afflicted Raptor Cove in the last generation of Intel desktop chips, (page 2)

I don't think the area comparison of LNC vs RPC makes much sense. Lion Cove is on a significantly denser node. If one wants to make the claim that LNC solved much of Intel's area problems relative to the competition, which I also think is true anyway, a comparison vs contemporary cores in the same node class makes more sense IMO.

That challenge is significant because Skymont has a lot of catching up to do if it wants to step into the P-Core role. Skymont is a huge step up from the earlier Crestmont and Gracemont, but it still has less reordering capacity than Lion Cove, a weaker vector/FP unit, and much lower clock speeds. (page 3)

Idk if having a lower capacity ROB is inherently worse, if you are able to achieve similar IPC as cores with larger ROBs. Hasn't that been the trend with Intel's E-cores anyway?

What's interesting about frequency is that the E-cores also appear to have a good bit higher OCing potential than the P-cores too. And I doubt simply relaxing the area constraints of the core won't allow for higher clock speeds too. After all, Skymont's area allocation is tiny.

I'm actually going to bring in Zen 1 as an example of what Intel wouldn't want to happen. Zen 1 was a solid core, but could not match Skylake in single threaded performance despite launching years later. (page 4)

I mean wasn't AMD already very behind Intel in ST perf anyway? Them not being able to close the gap in one gen, even if it was a large rework, is hardly a knock against it, especially since AMD was still using a worse node than Intel.

AMD lowkey flamed Global Foundries when at ISSCC when they compared cluster area vs Intel while also pointing out that their node was just less dense and they used fewer metal layers.