You can go try out ARM's assemblers for their 32 bit platforms. It changes instructions all the time. As long as all the effects are the same. Some types of instructions don't even exist on ARM, they are pseudo-ops for other things. Their assembler really got moving with Thumb (their compressed instruction set) because there are more compressed versions of some instructions than others and some duplicate encodings are removed.

They are only carrying on what other architectures and assemblers have done over time. 68K assemblers would change ADD with an A register as a destination to ADDA because ADD to an A register was illegal. Also write ADD #6, D0 and it would be assembled to ADDQ #6, D0 because it was a smaller encoding.

And if you think about it you can work out why it is like this. Think, why wouldn't you just write ADDQ instead of ADD in the first place? That's totally find if you are writing literally ADDQ #8, D0. But assemblers are symbolic. What if you write ADDQ #(DVAL/4), D0? It assembles the first time because DVAL is 32. But what happens when DVAL becomes 36? Now DVAL/8 is 9 and you can't ADDQ 9 to something. So you always write ADD #(DVAL/4), D0 and every time it fits in an ADDQ the assembler generates an ADDQ and when it doesn't it becomes an ADD. You are still free to write ADDQ.

RISC-V goes even further, it would make ADD #8, D0 (note, such an instruction does not exist, it's an example) an illegal encoding since there is already an encoding for this operation. So without the optimizing assembler writing assembler would be much more difficult.

On MIPS the default assembler mode (IIRC) was that you wrote your code in order and then the assembler would rearrange to put instructions in the delay slot (MIPS would run the next instruction after a branch regardless of whether the branch was taken or not).

You can look up RISC-Vs pseudoinstruction lla if you want. Or la, which turns into lla or lga, neither of which are instructions either. Better yet, look up their far branches transformation. It shows the same as ADD/ADDQ for 68K. If the branch fits in a single instruction it emits a single instruction. Otherwise it reverses the branch and emits 2 instructions. Their example:

target:
bne a0, a1, target
.rep 1024
nop
.endr
bne a0, a1, target

0: 00b51063 bne a0,a1,0 <target>
...
1004: 00b50463 beq a0,a1,100c <target+0x100c>
1008: ff9fe06f j 0 <target>

https://zju-os.github.io/doc/spec/riscv-asm.pdf

See page 42 for more transformations.

For 68K, ARM and RISC-V I don't know there are any settings for optimization for the assembler. As I mentioned I think the MIPS assembler did have a setting to turn off the delay slot automatic rearrangement.