ASML says first chips made with High-NA EUV machines to arrive in months
Posted by sr_local@reddit | hardware | View on Reddit | 38 comments
Posted by sr_local@reddit | hardware | View on Reddit | 38 comments
involuntarynewb@reddit
I know TSMC said they are not purchasing one of these machines because they are too expensive right now. But might that be because they do not feel entirely secure at the moment?
They do not have an option to utilize this machine outside of Taiwan right now. Aside from the 400 million dollar pricetag for one of these machines, do we have an estimate of what it would cost to retool one or a portion of their fabs to utilize this tech?
I'm curious as to how they are measuring "too expensive". An enormous investment with tensions high could be catastrophic to the company should anything go down on mainland Taiwan. Intel and SK Hynix ready to adopt this, so their decision to sit out for a while is a little puzzling.
Seanspeed@reddit
TSMC can afford it, I think a bigger concern is scaling. TSMC are the king cutting edge chip providers out there, and so need to be able to promise huge volumes of chips to multiple major tech companies. High NA machine manufacturing is still only slowly ramping up and ASML can only provide so many units, especially when TSMC has to compete with Intel for machines.
Spirited-Sale-3711@reddit
anyone who wants to spend the money could order an EXE 5200 right now. putting one at IMEC is pretty clear evidence that the current demand has been met.
involuntarynewb@reddit
IMEC is in a strategic partnership with ASML, the EU, and several other European countries (though oddly not with the Netherlands). So it makes sense that they have the cash and they'd get fast tracked to obtain one. Most likely with some nifty gov financial incentives.
Spirited-Sale-3711@reddit
yea, they had a proto version of the NXE (low NA tool) at IMEC for early development work. for the NXE (high NA tool) there is a tool at ASML that was called out as the joint ASML / IMEC development tool. ASML expected significant demand for the EXE starting in 2024, but that did not materialize (just ask anyone linked to the EXE supply chain how that has gone for them...).
given the yield concerns around the litho stitching process required on the EXE for larger die (like the AI related chips from Nvidia), having a tool at IMEC will enable better/quicker characterization and development of that process. IMEC has the KLA inspection tools, defect review SEMs and other systems needed for this work.
the alternative to the stitching process would be to go to 12x12inch reticles, but that will require changes across a large swath of the supply chain and the EXE tool. it does not sound like ASML wants to go down that path.
Seanspeed@reddit
There is never any such thing as meeting demand for these cutting edge machines. lol
I would guess any machine at IMEC was likely a prototype, not a properly functional machine they are just holding back on for funsies.
Spirited-Sale-3711@reddit
tool #1 was the joint ASML / IMEC tool at the ASML factory. the tool going to IMEC will be like tool #8 or so. ASML & Zeiss have material for like 3x that number of tools. so yea, current demand has been met.
soggybiscuit93@reddit
TSMC operates the largest EUV fleet on the planet. It's in their best interest to get the most out of those machines that they can, and see how far they can take 'em.
Other fabs, like Intel on the other hand, have a fairly small amount of EUV machines, and at this stage in the game, it would make sense to try and early-adopt High-NA rather than start procuring a bunch of new EUV machines that may only have another 2 - 3 gens of node shrinks left in them.
UpsetKoalaBear@reddit
Would probably be Samsung or SK Hynix if I was to guess.
Intel isn’t planning on 14A until next year, so can’t be them.
sussy_ball@reddit
Isn't Intel 18A made using High-NA EUV machine? It's written in their website
UpsetKoalaBear@reddit
Not for 18A (their current node).
They do have high-NA EUV machines, but they are planning to use them in 14A next year.
grumble11@reddit
Looks like 14A might not have chips on the market for two years
Pale_Ad7012@reddit
Intel was the first one to buy high NA machines
Kougar@reddit
Ordered in advanced, not the same as delivered. The first machine Intel installed was at their R&D D1X fab as it's an R&D model, not intended for mass volume production. Intel only installed its first 5200B mass volume High-NA machine last December, and one machine isn't enough to run a node off of. Intel announced a year or two ago that it would only utilize High-NA for the most complex steps in its 14A node.
The article mentions memory, not just logic. So I'm pretty sure they're referring to SK Hynix which was the first to install a 5200B and get it up and running. Reportedly it was going to be used for development and R&D rather than mass volume, but it's capable of doing both.
UCSDThrowAway45@reddit
Intel was the first to have a 5200B installed and up and running (they now have 2). You may still be right on whos producing with it but wanted to correct that.
Kougar@reddit
Tom's not being particularly good with the titles as usual, but SK Hynix got their 5200B up a quarter before Intel did. As for the "second" one, you may be thinking of the vanilla 5000 which Intel got running back in 2024, which is the R&D only machine in Hillsboro so I don't count that one.
UCSDThrowAway45@reddit
Not really sure how that article is qualifying their statement, but the first 5200B was built and transferred to Intel, then SK, then a second to Intel
Spirited-Sale-3711@reddit
yep. Intel has a 5000 (tool #2) and two 5200s. Samsung has a 5000 and ordered two 5200s (which rumors are they tried to cancel). TSMC and Hynix have a 5200. and IMEC is getting a 5200.
Exist50@reddit
IIRC, they got some of the first batch, but there was never a claim they bought the full run.
Anyway, we know they're not using them for a couple years yet.
UpsetKoalaBear@reddit
It’s very much an inverse of what TSMC and others did back in 2017ish when they bought up most of the EUV machines, meaning Intel didn’t get theirs until 2022. It’s part of the reason they fell so far back around then compared to AMD.
TSMC is still cautious on High-NA, and I think they know what they’re talking about but it is definitely a huge gamble. It will be interesting to see how it plays out.
Exist50@reddit
That claim seems just outright false. Intel had machines earlier than that. Remember that Intel 4 (or I guess technically p1276.2) was supposed to be ready for volume production by EoY 2021, and they'd presumably need the tools a solid year+ earlier. So either Intel voluntarily delayed receiving them because of the Intel 4 slips, or they had many more before that article was published. Keep in mind that Ireland is not Intel's only site.
Not really. They couldn't get a 7nm-class node working, and TSMC did that without EUV.
UpsetKoalaBear@reddit
Intel were involved in EUV development, just like Samsung, TSMC and other fabs. It was a research project across many different companies.
However, they had a lot of issues acquiring EUV machines because of the backlog.
They only had 3 development fabs in 2022 in Hillsboro and 1 EUV production fab which was the Ireland fab I linked before.
Exist50@reddit
There is no reputable source for the claim that Intel could not source a meaningful amount of EUV machines before '22+. Again, they outright planned to be in volume years prior. So like I said, either you believe they lied about that timeline from Day 1, they voluntarily delayed receiving shipments, or they did have machines but they were sitting idle.
UpsetKoalaBear@reddit
The link I sent is from Scotten Jones at SemiWiki.
I fail to understand how exactly it isn’t reputable. That is one of the most highly reputable sites for semiconductor news.
He outright says:
“Intel currently has 3 development fabs phases that are EUV capable and 1 EUV capable production fab although only the development fab has EUV tools installed. Intel is building 8 more EUV capable production fabs.”
That was published in 2022.
Exist50@reddit
The specific claims are different. They may not have installed the machines until then, but that's different from not having them or not being able to get them.
Capital-Froyo-4359@reddit
The whole narrative that TSMC isn't using high-NA is so overblown. They have acquired seceral units and are testing them. Their first high-NA node is only a year behind Intel. They're being slightly more conservative, not just completely ignoring the technology.
Seanspeed@reddit
I dont think we know any hard details. But from recent comments from TSMC, it sounds like they're still a bit farther out from using High NA for commercial chip production than just a year.
GenZia@reddit
Coming soon to a datacenter near you.
Capital-Froyo-4359@reddit
Certainly not. High-NA has reduced chip size which is a non-starter for datacenter chips.
Seanspeed@reddit
They can do it, they're just gonna have to design heavily around on-package interconnects and have like 4x(or more) compute tiles or GPU titles on each overall GPU/accelerator.
So it will be a shift for Nvidia who are used to going near reticle limits, but they're already clearly advancing with on-package interconnects. AMD are already basically there, though. MI300 and MI300X use like 6-8 of these compute tiles, all of which are well within High NA's lower reticle limit die sizes.
ComplexEntertainer13@reddit
Size is irrelevant, what matters is transistor budget. It only really is when you are just 1 node behind where going with the larger and less dense chip is still a option.
More than that and the increased density will offset the smaller reticle limit.
Capital-Froyo-4359@reddit
In theory that's true, but we aren't actually doubling in density each node any more. So 50% reduction in size with 15% increase in density means 43% less transistors than on the older node.
ComplexEntertainer13@reddit
Which full node jump that didn't include a transistor change offered only 15% density?
Neither are we getting just 15%. Make sure that you are actually comparing the full node jumps. Rather than the current naming schemes and node refinements the industry launches these days that are all over the place.
Capital-Froyo-4359@reddit
N3->N2 is 15%
ComplexEntertainer13@reddit
Not first implementation of N3.
III-V@reddit
They stich everything together using emib now.
Seanspeed@reddit
Well as far as Nvidia goes, they dont seem to jump on the latest and greatest node right away in general, plus they mainly use TSMC which aren't using High NA. AMD as well relies basically entirely on TSMC.
UpsetKoalaBear@reddit
Yeah, Nvidia’s die limit is definitely going to be a factor for them.
Blackwell was delayed last year (supposedly) due to issues with their die size.
My theory is that Nvidia will switch from CoWoS-L to something like InFO which was used by Apple and continue to use N3.