While I agree that the lack of ECC by default is a sad state of affairs when every other modern bus has it, it does significantly add cost: you need extra physical DRAM chips to implement it because of the redundant data. It’s not just bus overhead taking a bite out of your bandwidth.

Like you said, consumers don’t care, and Intel desktop platforms don’t even support ECC anyway. In any case, DDR5 already has on-die ECC that works transparently, mostly to improve yields. It won’t report errors (as those are going to be routine) or detect in-flight corruption, but should catch random bit flips from cosmic rays or whatever.