I think the thing that concerns me is the article also mentioned that roll on hard masks and temporary adhesives used in hbm production might get affected. THIS is really bad (id argue this is more concerning than euv getting affected) because this will affect processes that are extremely crucial to anything that uses vertical ic stacking/3d heterogeneous integration. In other words basically all modern memory including hbm. This will also affect logic to an extent like amd X3D cpus since similar processes are used to allow for amd to put 3d v cache on the same subtrate as the logic die.

Hard masks are super important because they have a significantly higher silicon etch selectivity than photoresist (in english this means higher etch resistance). For anyone that isnt familiar with semiconductor manufacturing, you need your mask or pattern to be resiliant enough to hold its shape through whatever process youre going to do after lithography whether its etching, deposition, etc. And generally speaking the mask is not 100% resistant to etch processes and will be affected alongside whatever silicon youre trying to etch.

This is where hard masks come in handy. They are commonly used in memory production because you need to be able to etch super deep trenches that you then deposit other materials in to make something called through silicon vias (TSV). TSVs are what allow you to stack chips on top of each other vertically enabling things like HBM and having memory on the same substrate as logic (like AMD 3d v cache). Photoresist alone is generally not sufficient enough to last through a deep reactive ion etch without getting destroyed unlike a hard mask. And since hard masks are able to hold their shape through intense etch processes you can get deeper features AND higher resolution features so you can cram more shit into the same area.

Sorry for the yap im a uni student whose research interests are heavily related to memory production so i wanted to share this tidbit.