TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027
Posted by Geddagod@reddit | hardware | View on Reddit | 30 comments
EmptyVolition242@reddit
So does the N2U node that will go mainstream be an upgrade over N2P or even N2X?
Geddagod@reddit (OP)
Over N2P, TSMC is citing slight PPA uplifts for N2U. Against N2X, it may be more design specific.
EmptyVolition242@reddit
That's good to hear. Apple with the N3P node already is massively efficient in single core performance, and adding N2U which would be a node++ upgrade, it's nice to see it go in the cheaper mainstream.
Geddagod@reddit (OP)
Nvidia Feynman is the only product so far rumored to use this node afaik. However, that's also expected to launch in 2028, so this move kinda makes sense.
Verite_Rendition@reddit
NVIDIA is a huge customer. But still, a cutting-edge node that's only used by a single customer? I have a hard time believing it.
Hanselltc@reddit
a cutting edge node that's only used by a single customer? thats half their nodes in the last decade, with the single customer being apple. the unusual thing here is the single customer being nvidia instead of apple, not that there is a single customer.
Verite_Rendition@reddit
Huh?
Just taking a quick rundown of nodes Apple has used.
And that's just the last four generations.
Now if you're saying that Apple starts out as the first customer using all of these nodes, sure, that is accurate. But the OP was claiming that NVIDIA would be the only company to use A16, which is quite a bit different.
Paed0philic_Jyu@reddit
It might be true if other customers see A16's BSPD bringing mediocre gains for the price TSMC wants for it, and Nvidia would in theory prefer exclusive access to a node, being the only customer who can spend that much $$$ for exclusivity at present and maintain their high gross margins.
-protonsandneutrons-@reddit
TSMC having the years is a little tricky to parse. N3P and N2 are both “2025”, but N3P products released in Q3 2025, but N2 only hit volume production in Q4 2025.
https://www.tomshardware.com/tech-industry/semiconductors/tsmc-begins-quietly-volume-production-of-2nm-class-chips-first-gaa-transistor-for-tsmc-claims-up-to-15-percent-improvement-at-iso-power
TSMC claims N2 has twice the tapeouts in the first year compared to N5.
Geddagod@reddit (OP)
Honestly I'm a little dubious of this. There haven't been any products on this node launched yet, and if nothing launches during computex... what exactly were they ramping?
Yea seems very popular.
FS_ZENO@reddit
Well I assume that’s when they started making chips on N2. Obviously it takes months to fully finish a chip so it makes sense. Plus they would need to build inventory before launch. First N2 products released is probably gonna be Venice/zen6 and mi400. It should be announced in computex to make sense
Geddagod@reddit (OP)
I don't think it takes them 3 full quarters for them to go from HVM start to product launch though.
Yes, I agree.
FS_ZENO@reddit
Technically it just depends on when the company wants to release it, I could see it make sense with the ai gpus so ai bros can pay a fuck ton to get it asap but it’s not like this time of the year is the time for product releases. And to reiterate on that, using Apple as an example, it not like Apple is gonna release their A20/M6 on N2 right right when they have sufficient amount of inventory, they always release their new iphones and stuff in September/fall so right now they’re building up inventory for that.
On another note, A16 slipping to 2027 means 2027 products will have to use N2P, which is normal as usual but the previous roadmaps had both N2P and A16 this year which made the N2P in a weird position where you can just use A16 unless you can’t pay for it. That previous roadmap gave potential to jump 2 nodes instead of the usual 1 lol, imagine going from N2 to A16 instead.
Due_Calligrapher_800@reddit
You can’t “just use N2P” if you have a design for direct contact BSPD on A16. They are totally different design rules & architectures that are not interchangeable. If you are designed on A16, it means your product is not coming out until H2 2027.
FS_ZENO@reddit
Yeah I know. Im sure chip designers knows more on whats TSMC's latest status on their future nodes than the public. But using the previous, outdated public roadmap as a theoretical scenario, if you were a chip designer and both N2P and A16 were gonna be HVM at the same year, if money is no problem then you would logically choose designing the next chip to built with A16 in mind rather than N2P for the next year's product(assuming your product comes in H2)
Due_Calligrapher_800@reddit
No. It depends on your use case. You aren’t going to be using A16 for a mobile chip for example. They are totally different nodes targeted at very different customers. A16 is for Nvidia, AMD, potentially ASICs who can make the most of the reduced IR drop and liquid cool the significant backside heat spots
FS_ZENO@reddit
Interesting, thats news to me. A16 is not for mobile chips? Surely theres still some gain in it even if it its not economically viable(even though theyre rich). What would mobile chip designers use then going forward? Unless future nodes like A14, 13, 12 can be also made for mobile chips? In that case, mobile chip designers would have to stick with N2P for 2 gens at least.
Due_Calligrapher_800@reddit
There is very limited gain to using backside power delivery for a mobile chip. Its primary use case is high performance compute where the benefits of backside power can really shine (reduced IR drop, decluttering of signal lines, more consistent & smooth power delivery). The disadvantage is that in order to get the most out of backside power, it creates significant heat spots on the backside of the chip which would previously have been dissipated through the silicon. This can be remedied primarily with liquid cooling which is most convenient for data centre GPUs & CPUs. It’s not convenient for a thin mobile product where you have thermal constraints as you’ll have to dial back the power significantly to avoid throttling. New thermal solutions are in development but until then backside power does not make sense for thin and light mobile chips as you can’t get the most perfomance out of them.
Intel is going all in on backside power, where as TSMC are keeping two separate process lines for FSPD customers (N2, A14) and BSPD customers (A16, A12)
FS_ZENO@reddit
Hmm, I guess we'll see what TSMC does beyond A12, if they release a node for FSPD and BSPDN per year since in that case, N2P to A14 is a 2 year gap(if thats a transition outlier) and then "returns" to 1 year with A13 going forward.
Is the gains from N2P vs A16 just from BSPDN? Wonder whats the gains/losses if you were to do HPC A16 to HPC A14 then.
Due_Calligrapher_800@reddit
Correct. A16 is N2 with backside power instead of frontside power. The actual node jump is N2 to A14.
I think A14P may have backside power but I’ll need to look that up as can’t remember off the top of my head.
BSPD is the future and once ways are found to cool mobile chips with effectively it is going to be the only way forward. TSMC are just keeping a FSPD line going until that day comes.
FS_ZENO@reddit
Wow, so technically the next BSPDN for A16 can technically jump 2 "nodes" assuming A13 and A12 is basically the N_P refinement node for A14 with A12 being the BSPDN version of A13, then if A14 doesnt have BSPDN and have to wait for A12, then youd be jumping 2 nodes going from A16(N2), skipping A14 and straight to A12(A14"P")
Then I guess for right now, BSPDN technically has an extra "nodes" worth of performance compared to FSPD when you look at N2P vs A16. Well it remains to be seen how HPC on A14 would perform vs HPC on A16. If its similar then that confirms it.
Due_Calligrapher_800@reddit
Yup. Nvidia is full porting to BSPD from Feynman onwards because they know the advantages are clear
FS_ZENO@reddit
Yeah then it kinda reminds me of like a similar situation with AMD's X3D, zen 5 may be some sort of outlier but previous gen X3D usually matches the current gen non X3D(As seen with 5800x3d vs zen 4), X3D can "easily" give arch's worth of performance within the same gen which puts it in a weird position just like with TSMC nodes.
You can create an illusion by getting an extra gen's worth of performance only because of the weird position because once it becomes "standard" the gains per gen will look like normal(although you can compare x3d vs x3d as generations) but theoretically if AMD made X3D the minimum standard and ditch "non X3D", just for that generation AMD can get "2 gens" worth of performance, one from arch/node and one from the cache. but then after that generation it will return back to the usual 1 gen improvement per gen.
Like once the industry moves to BSPDN then the gains will go back to the usual. Since right now it would feel like two if youre going from FSPD to new node + BSPDN like if you were to go from A14 to A12. It would be like A14 -> A14"P" + BSPDN, assuming it ends up being correct that HPC A16=HPC A14 in performance. Then that A12 would also equal a hypothetical FSPD "A10" or whatever. Also, the A14 is also in a weird position, for BSPDN to BSPDN jumps, not having BSPDN technically gives A16 2 node jumps to A12
knightofterror@reddit
TSMC is currently making hundreds of millions of 2 nm iPhone SOCs.
Geddagod@reddit (OP)
Yes, they prob have started HVM for Apple by now.... but it's been like 5 months since TSMC announced they started 2nm volume production. What were they ramping then?
TSMC for N5 and N7 have claimed they started HVM on those nodes at a similar time of the year as it is currently, and Apple were their lead customer. So it's a pretty easy assumption to make that whatever they were ramping at the very end of 2025 wasn't Apple chips.
mavere@reddit
N5 was 6 years ago btw. You've had several other datapoints since then for analysis.
Regardless, by this time last year N3P was already in production while HVM started late 2024. And let's just say we weren't flush with N3P chips on store shelves in April 2025.
Geddagod@reddit (OP)
The problem with using the N3 family, IMO, is how much of a mess the schedule was. The problems with N3B almost certainly incentivized TSMC to start lying about HVM readiness dates of nodes in that family to make it appear they are "righting the ship" faster.
We have an even better example with N2P supposedly being in HVM 2H 2026... and Mediatek announcing that they will have N2P products out this year.
It does not appear to take \~3 quarters of HVM for a product to launch. Intel regularly quotes shorted times as well.
TSMC's issue seems like they want to announce HVM when ever it might theoretically be possible or their yeilds are good enough... but their lead customer, Apple, just don't usually launch products mid year.
VastTension6022@reddit
It seems like it just didn't line up with product cycles; HVM ready for the mobile chips that typically lead but were already locked while not yet being ideal for the big DC stuff.
-protonsandneutrons-@reddit
It would be a really early start for Apple, the only rumored customer I can find. But maybe because there are so many customers for N2, Apple needs to start earlier to build up all the dies for A20 Pro / M6?
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