Intel's Nova Lake will unify L2 cache and feature new 'D' and 'DX' lines for enthusiasts, claims leaker
Posted by -protonsandneutrons-@reddit | hardware | View on Reddit | 9 comments
SirActionhaHAA@reddit
What's the point in having such a large number of cores when
Seems like a cinememe winning product which is impractical in real use.
Simislash@reddit
They're halo products, they're not expecting to move too many units. At the end of the day, the generic laptop chips make Intel/AMD the most money by a massive margin. These big desktop chips are meant to capture mind share and target performance users who sit somewhere between the typical i9 and server chips.
-protonsandneutrons-@reddit (OP)
Arguably, 99% don't fully load >8 cores. For most people, modern desktop CPUs have a gluttonous amount of nT perf. I suspect the 52C will be a halo product, sold in very low volume.
Many CPU manufacturers seek that "we're #1 halo", even if it means sacrificing power, cost, dies, energy, heat, logic, etc. Or also maybe like the 9950X3D2: "Because we can make a product some people will pay out the nose for."
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The raw GB/s per core will be lower than most recent CPUs. But NVL's fabric, caching and scheduling might allow the lower per-core bandwidth go a little further?
\~51 GB/s (JEDEC DDR4-3200, 128-bit) for 24 cores: \~2.1 GB/s per core (i9-13900K)
\~128 GB/s (JEDEC DDR5-8000, 128-bit) for 52 cores: \~2.5 GB/s per core (NVL-S 52C)
\~90 GB/s (JEDEC DDR5-5600, 128-bit) for 24 cores: \~3.8 GB/s per core (i9-13900K)
\~102 GB/s (JEDEC DDR5-6400, 128-bit) for 24 cores: \~4.3 GB/s per core (285K)
\~410 GB/s (JEDEC DDR5-6400, 512-bit) for 96 cores: \~4.3 GB/s per core (9995WX)
\~90 GB/s (JEDEC DDR5-5600, 128-bit) for 16 Zen5 cores: \~5.6 GB/s per core (9950X)
CatalyticDragon@reddit
The large amount of cache is intended to offset system memory bandwidth limitations.
The top of the line systems aren't aimed at 99% of users.
SkillYourself@reddit
Dude is just mad client Zen6 with its +50% MT stands no chance against dual tile Nova Lake.
hardware-ModTeam@reddit
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-protonsandneutrons-@reddit (OP)
4MB L2 shared between two P-cores was first rumored, AFAIK, back in June 2025.
-protonsandneutrons-@reddit (OP)
Recent shared L2 cache P-cores (many E-cores used shared L2, so I'm ignoring those)
Apple A16, A17 Pro, A18 Pro, A19 Pro: 16MB shared by two P-cores
Apple A15: 12MB shared by two P-cores
Apple A11, A12, A13, A14, A18, A18, A19: 8MB shared by two P-cores
Apple A10: 6MB shared by two P-cores
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Apple M2, M3, M4, M5: 16MB shared by four P-cores
Apple M1: 12MB shared by four P-cores
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Apple M5 Pro / Max: 16MB shared by six P-cores
I'm too tired to look up the rest, but feel free to add your own.
Sources: https://youtu.be/Y9SwluJ9qPI?t=445, Testing Apple's 2026 16-inch MacBook Pro, M5 Max, and its new "performance" cores - Ars Technica, Wikipedia
imaginary_num6er@reddit
I did not know tweaktown was allowed here