Samsung in Talks to Manufacture AMD’s Next-Gen EPYC “Venice” CPUs Using 2nm Process

> It definitely feels like an ego thing … Well, yeah. It definitely IS a ego-thing for Intel — They called them *Tiles* purely out of spite. Since you can't just call basically the very same what your competitor has, the same name, can you? That's not how Intel rolls nor would have ever done anyway, even if doing so, would've saves them a lot of engineering-pain in the arse, even more teething-problems and cost them years of falling back behind their only lone competitor … Truth be told, Intel's *Tiles* are basically in essence just Copy-Pasta: *A botched Copy'nPaste-job from AMD's chiplets*, yet relabeled as 'Tiles', just for Intel trying to pretend to have their "own" chiplet-esque implementation, even if it's basically the very same … Wanna hear a joke? When Intel back then around 2018 out of the blue announced their heterogenous *Mix and Match*-stuff (pretending, they'd already worked a decade on this by then), the actual effing PowerPoint-slides actually didn't even incorporated anything called 'Tiles' — *Called them* ***chiplets****!* Yet some big weak weasel's ego was hurt in Santa Clara, and they renamed it *Tiles* shortly afterwards. http://web.archive.org/web/20210923105815/https://newsroom.intel.com/wp-content/uploads/sites/11/2018/08/monolithic-vs-heterogeneous-infographic.pdf > … just copy Ryzen's super successful and ultimately quite straightforward chiplet-scaling strategy. They joke is, due to both of them share a cross-patent agreement, Intel even would've had access to AMD's patented stuff over everything chiplets — Chances are Santa Clara chose not to over license-fees, or spite … *That's how you're f–cked over by your own ego* — Rather throw years of potential lead into the gutter, instead of even *thinking* about having to share some meager percentage of profits of yours with others. That's Intel for you. A bunch of braggarts and loud-mouths, wo always think they can do and know better, yet fail nigh every single time and still can't bring themselves to be humble for once …

Well, I think Intel at least *tried* to copy AMD's chiplet-paradigm helplessly for the last couple of years … It seems that Intel was taken totally by surprise on anything Chiplets and got caught with their pants down (again), when AMD brought it this quick to market, when having worked on them for a decade plus. Though IF Intel would already worked on anything *disintegrated silicon* for said 10 years by then (like Intel claimed when announcing their heterogenous '*Mix and Match*'-approach around 2018), *Intel would* ***not*** *have needed +6 years for finally reaching a fairly comparable design-approach* only half a decade later in 2023 with Meteor Lake (also Arrow Lake, Sapphire Rapids, Ponte Vecchio). Since sure enough, all these disintegrated designs \*somehow\* brought Intel truly massive troubles engineering-wise and they had tremendous difficulties to overcome those for years — The years-long horror-stories over validation and dead-on silicon past tape-outs on *Sapphire Rapids* and *Ponte Vecchio* for example are testament to that … *Meteor Lake* was also everything but a performer. ---- The issue at hand for Intel was quite many-layered … * Intel hardly knew how to do it (despite claiming otherwise for years). *Shocker!* * Intel had no real equivalent to AMD's SuperGlue aka *Infinity Fabric*™ That's for sure the most striking one, obviously — The reason they had to wait for PCi-E 5.0 to become a thing, for "Intel's" *CXL* to finalize upon it (which in itself is basically just AMD's former *CCIX* in disguise as Copy-pasta anyway done out of spite). * Intel haven't remotely had adopted a design-strategy by then, which would've offered so to speak "intelligent" chiplets/tiles, which could be freely thrown together randomly at will on a (PCi-E) bus (which AMD actually evidently can with their CCX and I/O-dies since ages). So Intel's claims before the press in 2018, of already working on disintegrated silicon since years already (and that AMD *weren't* actually as spearheading as they became), was pure virtue-signaling, a blatant lie. As a result, Intel's IP-blocks still remained virtually *dumb* (in the sense of *head*|*less*) for years on out afterwards and most of it had to be *re-engineered from scratch* in all this other trouble like lay-offs, down-sizing or Intel's road-maps being constantly thrown out again (only to start over once more). The reason why AMD had a years-long edge on chiplets from the onset, was since Intel just couldn't place or handle the stuff as ***independent*** *IP-blocks* — Everything was grown intercoupled and -linked together. AMD on the other hand already had a decade-long headstart, due to their already well-tuned modular concept of IP-blocks (building-block principle with IP-blocks to freely chose from) attuned for the console-era from back then for the console-contracts (those, Intel always made fun of since). So Intel allegedly been working on chiplet-esque designs for years already, was utter bullsh!t, and that's actually the sole reason WHY Intel struggled so hard for years with anything Tiles — They started at 0.