From all truths to (ir)relevancies
Posted by Paddy3118@reddit | programming | View on Reddit | 4 comments
Just posted a follow-up to my blog post on truth tables! This time, I'm introducing the "Standardized Truth Table" (STT) format. Using the STT, I've developed an algorithmic method to find and remove "irrelevant" variables from a boolean expression. The core idea is simple: if changing an input's value doesn't change the output, that input is irrelevant. This is super useful for simplifying logic and making digital circuits more efficient.
firedogo@reddit
This was a fun read, truth tables are the Excel of logic, and you just added pivot tables.
A few ideas that might push it from "cool blog" to "tiny EDA tool":
Interchange formats, alongside your STT, accept/export PLA/BLIF (and maybe DIMACS CNF via Tseitin). That makes your tables plug into Espresso/Yosys for instant cross-checks.
Don't-cares & relevance, first-class support for - rows (care set / don't-care set) plus automatic cofactoring (F|x=0, F|x=1) and Shannon decomposition. Designers love handing you X's and getting area back.
Represent columns as a single Python int (2\^n bits). Then AND/OR/NOT are just & | \^mask--crazy fast and perfect for multi-output functions.
Allow lexicographic vs Gray code row order and make variable order explicit. (Saves "endianness fights" and makes Karnaugh maps line up.)
Property tests -- quick Hypothesis check that eval(expr) ≡ table for all inputs; then emit a tiny Verilog module and let Yosys do sat -prove for formal sanity.
lolimouto_enjoyer@reddit
I didn't understand a single word of this.
firedogo@reddit
lol
Paddy3118@reddit (OP)
Wow, are you in chip verification too😊 My interest is in another direction at the moment. I am looking into mining more of the verif and coverage data regressions produce to aid debug.