Intel Patent: Software Defined Super Cores

Posted by SherbertExisting3509@reddit | hardware | View on Reddit | 37 comments

Someone on the Intel subreddit found a patent about "Software Defined Super Cores"

Is this the long thought to be canceled Royal Core?

Seems like Intel restarted development of Royal Core awhile ago or they're developing RYC technologies to use on future cores designs.

Maybe this could be what they're planning for Hammer Lake?

Here's the abstract:

Abstract Techniques for software defined super core usage are described. In some examples, a fist and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program.

2024-11-26 Application filed by Intel Corp 2025-07-02 Publication of EP4579444A1

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MrHighVoltage@reddit

Probably they plan on renaming Hammer Lake to Hand Lake. Otherwise I don't really know what a fist core should be.

Jokes aside, how serious can a patent be with a typo in the intro.

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CommanderArcher@reddit

Introducing Intel Fist Core 9 370 HKJ

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SherbertExisting3509@reddit (OP)

I wouldn't want to jump in a lake of hammers

Sounds painful.

Jokes aside

Hobestly i don't think RYC will ever come back from the dead.

The core teams likely have their hands full with trying to finish the current designs that will keep Intel afloat

At best they will use some of it's technologies in future cores.

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MrHighVoltage@reddit

It sounds so complicated, for basically only limited gains. What we saw as a solution for this is simply big and little cores. Big cores for single threaded loads that need maximum performance, loads of little cores with higher performance/power and performance/area for multithreades loads. Without having the hazzle of dynamic runtime combining of execution units... that introduce latencies that really no one can afford these days. Especially not Intel.

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Exist50@reddit

The point of Royal was max ST perf. Anything else was just to recover area efficiency in MT workloads.

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MrHighVoltage@reddit

Yes. But this has more or less been solved by using heterogeneous setups. I can think that the additional area requirements to make this possible are vastly higher than actually building a few cores with more execution units and wider OOO etc... Already now modern CPU cores are mostly just control units, with the actual execution units just making up a smaller fraction of the overall area.

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Exist50@reddit

But this has more or less been solved by using heterogeneous setups

Heterogenous setups don't make the P-core any faster. It doesn't solve the ST problem.

Also, heterogenous doesn't work for datacenter. Even your P-core needs to have reasonable PPA.

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MrHighVoltage@reddit

Yes, but P-Cores are the cores for ST tasks. They only get faster by making them bigger and I suspect the additional latency of connecting two cores is actually making things worse.

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ResponsibleJudge3172@reddit

Do note that E cores have better latency in all scenarios than P core. And they are 4 a cluster.

The E core cluster to E core cluster can be half the P core to P core latency

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Exist50@reddit

What are you talking about? To be clear, the idea behind Royal was to make a high IPC, more modern P-core replacement. Nothing to do with combining cores.

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MrHighVoltage@reddit

Yes yes, I know that. Sorry I maybe was a bit unclear. What I meant is that probably the speedup is not that big, but the additional effort on hardware is huge. IPC in current CPU cores is mostly just a question of area. Of course, if you find a design, that suitably combines, let's say, two E-cores and makes one P-core with 60% higher the ST performance... perfect. But I doubt it. Let's see. In the end it would be amazing to see new solutions to old problems using reconfigurable hardware etc.

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Exist50@reddit

IPC in current CPU cores is mostly just a question of area

Eh, to a point. But if you look at shipping CPUs today, there are pretty significant differences in IPC per area. A lot comes down to how you do it. Just naively making existing structures bigger (what P-core was doing for long while, maybe even still is doing) ends up being inefficient.

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hollow_bridge@reddit

That level of latency wouldn't be an issue for most things.

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No_Sheepherder_1855@reddit

Wait I thought Reddit hates MLID?

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Geddagod@reddit

This has been a thing that has been worked on, and found to have been worked on publicly, long before MLID started leaking anything about RYC.

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No_Sheepherder_1855@reddit

Oh, where was it leaked previously?

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Vince789@reddit

There's been similar rumors since Intel acquired Soft Machines in 2016

Soft Machines claimed to have software defined virtual cores

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No_Sheepherder_1855@reddit

Interesting, I went back to a thread here that’s 9 years old and someone was claiming AMD was trying this 10 years before then. Guess it’s been researched for a while.

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Strazdas1@reddit

there i surprising number of things that have been started being researched 20 years ago but do not become economic to implement until now.

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Jeep-Eep@reddit

The reason folks still give him the time of day is that, sometimes, he does have legit scoops. Not often, but not enough to just totally dismiss him.

Granted, IIRC, his most reliable takes are vis a vis Team Red.

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kaxon82663@reddit

Just like software-defined radios (SDR), this concept is gonna be shit

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SovietMacguyver@reddit

I think a better comparison is virtualized memory management, which is wildly successful.

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ClerkProfessional803@reddit

This is an update to the soft machines patents intel purchased ages ago. Fusable Cores for higher single threaded ipc.

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Exist50@reddit

Another waste of money.

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Exist50@reddit

Doesn't sound like the Royal rumors to me. Royal was supposed to be able to have one large physical core be able to split itself to run multiple threads, more like CMT or SMT. This is basically the opposite idea.

Also, from a "will it happen" perspective, the answer seems clearly "no". Even forgetting the feasibility of the patent itself for a moment, look at the authors.

Jayesh Gaur - Left Intel Labs in January, now at IBM as Power chief architect.
Sumeet Bandishte - Left in March, also to IBM
Ariel Sabba - Used to lead Intel's P-core architecture. Left in December. Now leading Nvidia's CPU efforts.
Sreenivas Subramoney - Retired from Intel.

Does that sound like what you'd expect if Intel was actively pursuing the technology? Also, every rumor points to E-core being the basis of Intel's "Unified Core", not P-core, and the folk on this list seems to be a combination of Intel Labs and P-core. I think the data tells a story here.

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SherbertExisting3509@reddit (OP)

Can't edit the post so here's the first of 15 claims in the patent

"An apparatus comprising:

a first processor core to execute a first set of instruction segments of a single threaded program; and a second processor core to execute a second set of instruction segments of the single threaded program, wherein each of the first processor core and the second processor core is to include circuitry to support the first and the second processor core to operate as a single virtual core to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program"

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IAAA@reddit

Intel has somehow reinvented the Cell processor. It had this functionality.

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AttyFireWood@reddit

So core(thread) progression shall be: 1(1) to 1(2) to 1(1) to 2(1)? I'm being facetious

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ResponsibleJudge3172@reddit

If one didn't know better, the P core cluster of NovaLake looked like a good candidate for this.

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Cortisol-Junkie@reddit

Filing patents does not mean they plan to do anything with it, especially since it seems like this would need changes to software for the added control flow instructions and it's not a transparent micro-architectural change. But I am curious to see how this compares to just making a wider core. Will be quite surprised if this approach wins.

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HorrorCranberry1165@reddit

For better perf, they must employ APO that optimize code for better management of cache and use AVX512.

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RetdThx2AMD@reddit

Companies are incentivized to file for patents on anything they can. Usually employees are incentivized as well, where I used to work you got a bonus for patents. A patent filing can come quite a long time after the original work was done. It does not mean that the tech is actively being used, or even planned to be used. Just that they think it is patentable.

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Me and others here as PC Gamers obviously would've loved RYC but the PPA cost sadly didn't seem worth it which is why Pat killed it.

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Creative-Expert8086@reddit

Is LNL very terrible PPA as well?