No.

https://www.reddit.com/r/hardware/comments/1fr8ws8/snapdragon_x_elite_die_shot_revealed/

Note how the last Intel reference was RWC, an especially bad N5 class core in terms of area. Whether that be due to the worse node, Intel's older physical layout methodology, or whatever reason, they have significantly improves with LNC.

A LNC core without the L1.5 and L2 SRAM arrays alone is already the same area as a M4 P-core (actually I forget, I might have also included the tags in this area calc too lol), and that's not including all the logic that is associated with handling the core private L2 too.

As for Apple's N5/4 cores, it's important to remember that Apple didn't really start to compete with high end AMD desktop products in performance till their N3 parts. Zen 4 and Zen 5 both had 16 and 26% leads in specint2017 1t performance respectively according to david huang, making the area differences much more swallowable.

But I also want to point out- Zen 4 without the L2 block is outright smaller than a M2 core.

Apple offloads SIMD tasks to a dedicated AMX processor, NPU, GPU depending on the optimization. Since Apple chips will always have the AMX, NPU, GPU, they don't have to try to do everything inefficiently on the CPU. Software can be written with a guarantee that these components exist.

The problem is that for server processers, you don't have that option to offload it to those parts, and Intel and AMD have to incorporate AVX-512 or AMX as a per-core option, presumably for licensing, and also because it's just more performant.

So when looking at a core perspective, Intel and AMD obviously suffer from increased area from that while Apple does not. Something to keep in mind when comparing core area, especially considering the area difference does not seem to be insignificant-

For Zen 5, simply changing how AVX-512 is implemented causes a dramatic halving of the FPU block in desktop vs mobile for a 10% area reduction.

You should look at the whole die size of the SoC then compare its performance for CPU, NPU, GPU to get a higher level overview of performance/area since it's too difficult to measure accurately that includes all the caches and architectural differences.

If you want to just compare CPU cores, you wouldn't have to look at the NPU and GPU.

I think two important measurements would be just CPU core+L1, and then the "CCX" area.

The Core + L1 because the L1 cache is way more incorporated into the core than the higher levels of cache, by a large degree, and also because the later levels of cache have a much more disproportionate impact on perf/area.

For example, Intel nearly doubling the L2 cache from GLC to RPC caused a significant area increase, while only providing a low single digit IPC uplift in most workloads. The area cost of those caches as a percent of total core area is only bound to increase too, as logic starts scaling much better than SRAM.

There might be more obvious CCX level power benefits, or be significantly better in specific workloads that isn't really represented by spec2017, or be a "future proofing" case as working set sizes grow, but from a raw perf/area perspective, it's disproportionately bad.

And why measuring CCX area is good should be clear, and yes Apple does very well against AMD and Intel here, but as I alluded too in my previous comment, this is solely because of their unique cache hierarchy, which seems to be a product of Apple's design team (the same team that then moved over to Qualcomm, hence Oryon sharing a very similar cache design), not because of the "core" area.