"1.4 nm" doesn't sound like any public TSMC nomenclature I know of.
In the same TrendForce article which this news quotes from, which itself is presumably a paraphrasing of the original news article in Chinese, A16 is referred to as 1.6 nm and we know that A16 is supposed to enter risk production in late 2026.
That would mean Apple going through 3 'full-nodes' in 3 years - the 2025 iPhone which is rumored to still use N3, the 2026 iPhone using N2 and the 2027 iPhone using A16 - which is very unlikely.
And TSMC timelines in official presentations don't generally refer to volume production.
I'm specifically saying that there will be no volume production of A16 in late 2026, unlike the other clueless poster in this comment chain who doesn't understand physics, blindly applies formulas that are only empirically applicable in a narrow sense, and puts way too much emphasis on verbal claims made by executives instead of data presented by engineers.
That would mean Apple going through 3 'full-nodes' in 3 years
I don't think A16 is a full node jump. Seeing how it's apparently geared towards HPC as well, Apple might not even use it for their mobile chips at all.
And TSMC timelines in official presentations don't generally refer to volume production.
He also mentioned TSMC's A16 technology, which is scheduled to produce the first 1.6nm chips by 2026. This will be available with Super Power Rail, TSMC's version of the backside power delivery approach detailed by Intel, and the node is to feature a further 8 to 10 percent speed improvement at the same power compared with N2, and an additional 7 to 10 chip density gain.
"Volume production is scheduled for second half 2026," Wei claimed.
I don't think A16 is a full node jump. Seeing how it's apparently geared towards HPC as well, Apple might not even use it for their mobile chips at all.
Considering the claims about A16 over N2P involve the biggest relative reduction in power consumption at iso-speed, Apple has every reason to want to use A16, if they are considering it at all.
Considering the claims about A16 over N2P involve the biggest relative reduction in power consumption at iso-speed, Apple has every reason to want to use A16, if they are considering it at all.
It's weird though, because for those power and density claims, TSMC added an asterick of AI DC products. They didn't do that for their other power and density claims for N2, N3, and N5.
And even considering that, the perf/watt and density gains are still almost half that of what you would see out of even the N2 jump vs N3.
Meanwhile for devices that aren't HPC, apparently the advantage would be much smaller, and the cost penalty most likely won't be worth it, at least according to this on semiwiki forums.
I will stick with what is there in the roadmaps rather than rely on answers to analyst questions on earnings calls.
And I put full-node in quotes because full-nodes don't just refer to major PPA advancements but also introduction of new technologies - which according to Mark Bohr who you are a fan of - would be stuff like HKMG, FinFET, or in the case of A16 - BSPD.
Since shrinks from photolithography advancements are at the end of the road - unless hard X-rays find use in ASML machines - full-nodes essentially mean non-PPA advancements from now on.
So what about this roadmap makes you think they are referring to risk production here rather than mass production?
Also, I just checked, his comments about A16 timeline didn't come from answering a question about A16, but just the bog standard stuff they say during the earnings report before the Q&A starts. I believe he said this during multiple different earnings reports too.
I find it hard to understand why you wouldn't take the more recent CEO of TSMC's words about the timeline for A16, rather than a vague roadmap?
And I put full-node in quotes because full-nodes don't just refer to major PPA advancements but also introduction of new technologies
They really kinda do though. Doesn't matter if you add a shit ton of new technologies into your node if you don't gain any sort of tangible PPA benefit. Since in the end, that's really what ends up mattering to the customer.
which according to Mark Bohr who you are a fan of
And apparently like every analyst who uses his formula is a fan of lol
would be stuff like HKMG, FinFET, or in the case of A16 - BSPD.
I've been pretty consistent on the take that adding stuff like GAAFET or BSPD doesn't matter much if it doesn't lead into PPA benefits. Same reason you would see my many comments on how 18A isn't better than N2 just because it has GAAFET or BSPD, all just means to an end of better PPA.
Since shrinks from photolithography advancements are at the end of the road - unless hard X-rays find use in ASML machines - full-nodes essentially mean non-PPA advancements from now on.
No it does not. While we may have to revisit the density part of the "full node" gain especially, even the reported perf/watt gains are lower than normal, and those numbers again were just for HPC products, mobile products would see an even lower amount too.
Regardless though, this is mostly semantics about what makes a full node. TSMC says they will have it in mass production in 2026, and I think that's very possible, especially if they relax their PPA targets, which they appear to be doing, in order to get the BSPD implementation down easier.
I've been pretty consistent on the take that adding stuff like GAAFET or BSPD doesn't matter much if it doesn't lead into PPA benefits. Same reason you would see my many comments on how 18A isn't better than N2 just because it has GAAFET or BSPD, all just means to an end of better PPA.
Your opinion is irrelevant.
No it does not. While we may have to revisit the density part of the "full node" gain especially, even the reported perf/watt gains are lower than normal, and those numbers again were just for HPC products, mobile products would see an even lower amount too.
Again, your opinion is irrelevant. The very reason why shrinks are possible in the first place is because the wavelength of light in photolithography directly controls the feature size aka half-pitch, and EUV used in the latest machines is 13.5 nm while soft X-rays begin at 10 nm.
And drawing stuff with light is a diffraction-limited process.
Maybe in the large scope of things, sure, but seeing how many times you replied to me, it seems like my opinions are very relevant to you lmao
The very reason why shrinks are possible in the first place is because the wavelength of light in photolithography directly controls the feature size aka half-pitch, and EUV used in the latest machines is 13.5 nm while soft X-rays begin at 10 nm.
And drawing stuff with light is a diffraction-limited process.
What does this have anything to do with what I commented above?
If you just want to talk about lithography, I mean go off queen, but like what does this have to do with what you quoted me saying?
Regardless though, as I said here:
this is mostly semantics about what makes a full node. TSMC says they will have it in mass production in 2026, and I think that's very possible, especially if they relax their PPA targets, which they appear to be doing, in order to get the BSPD implementation down easier.
Doesn't matter much to me what constitutes as a "full node" vs half node in the end, TSMC at least officially claims A16 is going into volume 2H 2026.
I love how you just gave up on responding to literally the rest of my comment above too. But I mean, pick and choose your battles, right? Lol.
What does this have anything to do with what I commented above?
It has everything to do with your half-assed bullshit claim that full-nodes must have some arbitrarily large PPA improvement otherwise it isn't a full node.
Maybe in the large scope of things, sure, but seeing how many times you replied to me, it seems like my opinions are very relevant to you lmao
That goes both ways. Nobody is making you compulsively respond with verbose comments with little substance to every lukewarm-to-neutral thing I have to say about TSMC with your own rainbows and sunshine narrative, other than yourself.
Besides 1st April articles, ASML's newest lithography machine with higher numerical aperture, EUV High NA, pushes the transistors' critical dimension from 13 to 8 nm.
basil_elton@reddit
"1.4 nm" doesn't sound like any public TSMC nomenclature I know of.
In the same TrendForce article which this news quotes from, which itself is presumably a paraphrasing of the original news article in Chinese, A16 is referred to as 1.6 nm and we know that A16 is supposed to enter risk production in late 2026.
Geddagod@reddit
From what I've read online, A16 is supposed to enter volume production in late 2026.
basil_elton@reddit
That would mean Apple going through 3 'full-nodes' in 3 years - the 2025 iPhone which is rumored to still use N3, the 2026 iPhone using N2 and the 2027 iPhone using A16 - which is very unlikely.
And TSMC timelines in official presentations don't generally refer to volume production.
Kryohi@reddit
Volume production in late 2026 means no iphone chip on that node. Volume production would have to start in May/June for that to happen
basil_elton@reddit
Which node are you talking about?
I'm specifically saying that there will be no volume production of A16 in late 2026, unlike the other clueless poster in this comment chain who doesn't understand physics, blindly applies formulas that are only empirically applicable in a narrow sense, and puts way too much emphasis on verbal claims made by executives instead of data presented by engineers.
Geddagod@reddit
I don't think A16 is a full node jump. Seeing how it's apparently geared towards HPC as well, Apple might not even use it for their mobile chips at all.
Does seem to be in this case.
basil_elton@reddit
Considering the claims about A16 over N2P involve the biggest relative reduction in power consumption at iso-speed, Apple has every reason to want to use A16, if they are considering it at all.
I will stick with what is there in the roadmaps rather than rely on answers to analyst questions on earnings calls.
Geddagod@reddit
It's weird though, because for those power and density claims, TSMC added an asterick of AI DC products. They didn't do that for their other power and density claims for N2, N3, and N5.
And even considering that, the perf/watt and density gains are still almost half that of what you would see out of even the N2 jump vs N3.
Meanwhile for devices that aren't HPC, apparently the advantage would be much smaller, and the cost penalty most likely won't be worth it, at least according to this on semiwiki forums.
Errr why?
Also, what roadmap are you talking about again?
basil_elton@reddit
This one?
And I put full-node in quotes because full-nodes don't just refer to major PPA advancements but also introduction of new technologies - which according to Mark Bohr who you are a fan of - would be stuff like HKMG, FinFET, or in the case of A16 - BSPD.
Since shrinks from photolithography advancements are at the end of the road - unless hard X-rays find use in ASML machines - full-nodes essentially mean non-PPA advancements from now on.
Geddagod@reddit
So what about this roadmap makes you think they are referring to risk production here rather than mass production?
Also, I just checked, his comments about A16 timeline didn't come from answering a question about A16, but just the bog standard stuff they say during the earnings report before the Q&A starts. I believe he said this during multiple different earnings reports too.
I find it hard to understand why you wouldn't take the more recent CEO of TSMC's words about the timeline for A16, rather than a vague roadmap?
They really kinda do though. Doesn't matter if you add a shit ton of new technologies into your node if you don't gain any sort of tangible PPA benefit. Since in the end, that's really what ends up mattering to the customer.
And apparently like every analyst who uses his formula is a fan of lol
I've been pretty consistent on the take that adding stuff like GAAFET or BSPD doesn't matter much if it doesn't lead into PPA benefits. Same reason you would see my many comments on how 18A isn't better than N2 just because it has GAAFET or BSPD, all just means to an end of better PPA.
No it does not. While we may have to revisit the density part of the "full node" gain especially, even the reported perf/watt gains are lower than normal, and those numbers again were just for HPC products, mobile products would see an even lower amount too.
Regardless though, this is mostly semantics about what makes a full node. TSMC says they will have it in mass production in 2026, and I think that's very possible, especially if they relax their PPA targets, which they appear to be doing, in order to get the BSPD implementation down easier.
basil_elton@reddit
Your opinion is irrelevant.
Again, your opinion is irrelevant. The very reason why shrinks are possible in the first place is because the wavelength of light in photolithography directly controls the feature size aka half-pitch, and EUV used in the latest machines is 13.5 nm while soft X-rays begin at 10 nm.
And drawing stuff with light is a diffraction-limited process.
Geddagod@reddit
Maybe in the large scope of things, sure, but seeing how many times you replied to me, it seems like my opinions are very relevant to you lmao
What does this have anything to do with what I commented above?
If you just want to talk about lithography, I mean go off queen, but like what does this have to do with what you quoted me saying?
Regardless though, as I said here:
Doesn't matter much to me what constitutes as a "full node" vs half node in the end, TSMC at least officially claims A16 is going into volume 2H 2026.
I love how you just gave up on responding to literally the rest of my comment above too. But I mean, pick and choose your battles, right? Lol.
basil_elton@reddit
It has everything to do with your half-assed bullshit claim that full-nodes must have some arbitrarily large PPA improvement otherwise it isn't a full node.
That goes both ways. Nobody is making you compulsively respond with verbose comments with little substance to every lukewarm-to-neutral thing I have to say about TSMC with your own rainbows and sunshine narrative, other than yourself.
tia-86@reddit
1.4 nm sounds like a joke.
Besides 1st April articles, ASML's newest lithography machine with higher numerical aperture, EUV High NA, pushes the transistors' critical dimension from 13 to 8 nm.