Intel 18A and TSMC 2nm have same HD SRAM Density - ISSCC Conference Thread
Posted by SlamedCards@reddit | hardware | View on Reddit | 225 comments
Posted by SlamedCards@reddit | hardware | View on Reddit | 225 comments
mavere@reddit
I bet he's a poster here.
EstablishmentOdd5653@reddit
Classic conference Q&A moment—wasting the only question on naming semantics instead of actual technical insights. Would’ve been great to hear something more substantial, like cell stability, Vmin scaling, or yield expectations.
Vb_33@reddit
Why did they only have time for a single question?
GraXXoR@reddit
The guy was probably a “sakura” (someone placed in the audience for the express purpose of asking a question or directing the conversation)
Brilliant-Depth6010@reddit
Outsiders would like simplified industry metrics to guide their investment strategy. Insiders need talking points to convey information to (or just sway) outsiders. News at 11.
Helpdesk_Guy@reddit
You mean, like …yields? Or any other kind of indications about it and howsoever small bits on such. What a happy coincidence!
The mere fact alone, that Intel still desperately avoids showing any whatsoever indicator of their 18A's health, is all you need to know really, to further cement the fact, that 18A is still neither healthy nor fit enough, for any greater mass production nor means of HVM.
Make no mistake, but Intel trying to blind the crowd with fancy SRAM-numbers here (they boast to be able to achieve in any distant future), looks suspiciously familiar to what we've had seen since years – Talking about everything else, but yields.
While intentionally trying to light up as many side-shows as possible to distract from the fact, that Intel still after years of delays deliberately tries everything to avoid talking about the only uncomfortable truth there is: Their processes' health
The overall pattern is still the very same. Pretend that it's healthy just long enough, until it maybe actually is and Intel can finally deliver.
ProperCollar-@reddit
I'm sorry but we're too early in the game to be this concerned.
The warning signs on 20A were pretty clear but I disagree that 18A is unhealthy. We just don't know.
Helpdesk_Guy@reddit
It isn't remotely too early, when 18A was supposed to come out by 2H24 already.
It's way past due already! Especially any signs and valid indications of its actual health, which Intel still refuses to show.
Intel suddenly (yet nigh expectedly) knifing their 20A the moment it was supposed to come out, was not just a warning-sign.
It was the Iowa-Class' ship's alarm-bell for calling “Battle stations!” and all hands on deck during the day of attack at Pearl Habor!
The sole fact that Intel knifed 20A in September just mere *weeks* before its official release in October, evidently shows that Intel told everyone another blatant lie – Arrow Lake *had* to be unquestionably well in production at TSMC already for months by the time Intel announced the killing of 20A, due to the needed lead-time of literal months of such a release.
Adding to the obvious fact of a evidently needed lead-time in production of 3–6 months if everything runs according to plan (which it never really does) and it often can easily amount quickly to 6–9 months by any whatsoever greater difficulties;
Everything Arrow Lake had to be already well in production at TSMC for several months by the announcement of 20A's knifing!
Thus, by the time Intel announced the alleged knifing of ARL *publicly* (only to pretend to casually "switch" everything ARL over to TSMC) in September for said release in October (as obvious as it gets), Arrow Lake was already running off TSMC's manufacturing-lines well in advance to that date for months. Especially if you add the required time for re-routing ARL-dies to Intel itself, for Intel's additional packaging onto their literal Base tile-die on Intel's own 22nm FFL-process.
Yet sure enough, none whatsoever outlet (on Intel's pay-roll that is) was either capable (read: actually willing) to ask and dig, never mind asking any whatsoever probing questions regarding Intel's public highly-questionable announcement, to even remotely question anything of Intel's blatant lie and lame excuse on their pretended "knifing" of 20A in September.
Instead, 99% of all media-outlets just either sold it as instructed (95% probability) or otherwise have to be exclusively stuffed with utter fundamentally incompetent editors and writers which ain't having enough mental capacity, to come up with such probing question in the first place (80% chance for that being the case; making them out of place) – In any case, 99% of you all bought that story at face value and took everything what Intel touted as a fact to heart.
… which is exactly the very problem, my short-sighted friend! Even after two delays already and post past its first initially supposed launch-date, no-one still knows about nor wants to show any howsoever small indicator of 18A's health!
If that isn't telling you already more about 18A you ever needed to know, I don't know what should. Especially given the fact that Intel plays this lame game since their 10nm™ in 2015, and just repeats it every so often – People still fall for it to this day…
no_salty_no_jealousy@reddit
Found the guy who wasting conference Q&A sessions.
Helpdesk_Guy@reddit
Knowing Intel, that could've already also been easily a well-planned fabricated circumstance, to avoid nasty questions on matters of yields.
no_salty_no_jealousy@reddit
Found redditor who wasting ISSCC conference Q&A sessions. You are the biggest clown aren't you? 🤡
Geddagod@reddit
Holy shit dude take a break...
Helpdesk_Guy@reddit
Hate to break it to you, but the only one ought to finally have a break from their pattern, is Intel here. Same old, same old.
Geddagod@reddit
Intel has delayed some products, canned others, released mid stuff... but then they also had products that ended up ok, or even good, over the past couple of years.
I have never seen you comment anything good about Intel lol. Despite your massive volume of comments here. Add to that your tendency to go to random tangents while writing essays, it's not a great look....
no_salty_no_jealousy@reddit
I won't be surprised if it was one of redditor from r/hardware because a lot of people in here is so f**king dumb!!
EstablishmentOdd5653@reddit
Classic conference Q&A moment—wasting the only question on naming semantics instead of actual technical insights. Would’ve been great to hear something more substantial, like cell stability, Vmin scaling, or yield expectations.
TheCatholicScientist@reddit
At same conference. Someone asked the IBM guy during a talk this afternoon about those. He said he wasn’t allowed. Bet Intel guy was in the same boat.
mHo2@reddit
Yep lol, was surprised they even asked.
why_no_salt@reddit
As it they were allowed to talk about facts instead of being given some pre-approved marketing material.
Strazdas1@reddit
this is the result of not gatekeeping.
mHo2@reddit
heh lots of questions at ISSCC didnt really need to be asked.
Some guy asked the IBM Telum II guys what their yield was lmao.
iDontSeedMyTorrents@reddit
Oh boy that is embarrassing.
Famous_Wolverine3203@reddit
Who let the redditor into an ISSCC conference🥲
05032-MendicantBias@reddit
If that's true I'm pleasently surprised!
I was expecting parity with N4 at worst, and parity with N3 at best. If 18A can deliver parity with N2 we are in for a ride!
theQuandary@reddit
Way too many people here have been pushing Intel FUD for the past few months and clouding up the water.
I wonder how many have money invested in their position....
no_salty_no_jealousy@reddit
Way too many!
Honestly i've seen many of them are just bunch of redditors from amd stock sub who keep spreading non sense about Intel because they want to change market interest and P/E ratio. Those people are literal trash who ruined this sub!!
skinlo@reddit
This sub is fine.
throwaway223344342@reddit
It has been very suspicious to see what feels like a massive FUD effort.
Don't get me wrong: the last 10y at Intel have been rough, but we're starting to see upside. Lunar is a good product, Meteor-H is a good product, graphics looks healthy (die size a little big), Panther builds on Lunar, Nova Lake looks very compelling. That looks like a turnaround to me.
All of Intel's disclosure cadences are pretty consistent with what we typically see of them. If Panther is coming end of '25, then I would expect major process disclosures in (roughly) May/June at Intel's annual client ITT event for media. And everything we've seen so far looks pretty healthy.
grahaman27@reddit
Plus backside power delivery support means 18A chips are going to have the advantage in performance
Famous_Wolverine3203@reddit
There’s more to performance than BPSD, but we’ll see.
ExtendedDeadline@reddit
Of course there is, but BPSD is strictly an upside.
eding42@reddit
Not really strictly, it’s good but there’s definitely a hit to cost/complexity as you have to drill TSVs and use carrier wafers etc
ExtendedDeadline@reddit
Sorry, I should have added "to the end performance/efficiency". It certainly adds complexity.. But we're basically in the "everything is complex" phase of semiconductors.
Tiny-Sugar-8317@reddit
Still, it seems 18A is the most complex process ever built which is why all these rumors of poor yields ring true.
ExtendedDeadline@reddit
People just want to believe in their biases.
Tiny-Sugar-8317@reddit
It's not a bias to say increased complexity can reduce yields. That's just an objective fact.
ExtendedDeadline@reddit
Every new node with increased density/reduced size is the newest "most complex" semiconductor process. Every new node increases complexity, somehow. And, yet, yields remain on track.
Let the engineers do their jobs, let the yields at time of mass production speak for themselves, whatever they may be.
Anything beyond that is just letting biases and imaginations speak in place of hard data.
I'll also note the above isn't always true - TSMC has done node shrinks before that were also less complex because they could eliminate masking steps. Flip side is they were using more complex tech elsewhere to enable that --> but it was tech a different company figured out for them (e.g. EUV).
Tiny-Sugar-8317@reddit
You've missed the point. 18A is arguably more complex than N2 while also being lower density. That's not a good look.
ExtendedDeadline@reddit
Same density, and other performance benefits from the additional complexity.
The main point remains: "People just want to believe in their biases".
Tiny-Sugar-8317@reddit
Same SRAM density (according to Intel), but not logical density.
ExtendedDeadline@reddit
Your tone and short term post history really suggests otherwise, but okay.
Tiny-Sugar-8317@reddit
You do understand we live in a world of objective facts right? And you realize that in thst world Intel is getting it's ass handed to it in every single front? Saying Intel is doing terrible is just acknowledging reality. Not sure what that's so hard for you people to understand.
ExtendedDeadline@reddit
You love saying this. You repeat it in most of your posts. I'm lowkey wondering if you're a bot at this point?
What kind of fact is there that's not objective?
eding42@reddit
Arguably going from bulk to FinFET was a bigger change than to gate all around
Tiny-Sugar-8317@reddit
It's both GAA and BSPD at the same time though. And no low volume test node (20A) to work out the kinks.
Tasty_Toast_Son@reddit
Indeed, and it seems to take a couple process nodes for changes to materialize. I don't recall Ivy Bridge being much more than a side grade to Sandy Bridge's planar FETs back in the day. Nowadays, FinFETs have obviously pulled ahead leaps and bounds.
eding42@reddit
I mean objectively true that it’s the first to implement BSPD and nanosheet but not sure about the rumors about yields, both Tech Insights and Ian Cutress have the yield numbers unofficially and they both say that it’s actually quite healthy.
Maybe for 20a but I think the extra year definitely helped.
Tiny-Sugar-8317@reddit
Who knows, this all seems a little sus. We had negative 18A rumors for the past 18 months and then all of a sudden this month you have these two positive stories right as the breakup rumors are reaching fever pitch. It sure seems like these "leaks" are intentional to try and stop a breakup.
PainterRude1394@reddit
This is the problem when people don't understand what they are reading or what's happening but want to parrot Intel bads. This isn't a rumor.
Tiny-Sugar-8317@reddit
It's also a VERY VERY specific data point that people are massively exaggerating the significance of (if it's even true).
PainterRude1394@reddit
Do you go through these emotions every time there's a non negative story about Intel?
https://www.reddit.com/r/hardware/s/Pd67wP8j74
You took all the random rumors way too seriously and now neglect hard evidence because you want to keep pushing Intel bads. What a weird position.
Due_Calligrapher_800@reddit
This isn’t a leak? This is an academic paper presented at a conference. TSMC literally presented before them in the same room. Or are you referring to something else?
Kryohi@reddit
Whenever I hear about "18A performance" all that comes to mind is the furnaces that were raptor lake and its refresh. Intel needs efficiency, density and volume, not max perf. And I hope they're getting there.
Famous_Wolverine3203@reddit
Raptor Lake was on Intel 7. There’s like 3 node jumps since then.
Kryohi@reddit
I never claimed otherwise.
And yet no consumer CPU on an Intel node has been launched since then. The ones on 18A will be the first ones.
They need to deliver, even if they might have a slight efficiency or density disadvantage.
Famous_Wolverine3203@reddit
Actually, no. The next consumer PC CPUs are Nova Lake on N2P. Intel nodes are slated for mobile and data centre.
eding42@reddit
I thought Nova was on 18a-P?
Famous_Wolverine3203@reddit
Nova Compute is on N2P. The iGPU and SoC tile is on 18A-P.
eding42@reddit
I see, would this be the first iGPU product on Intel silicon in a while?
Famous_Wolverine3203@reddit
Some low end PTL parts are on Intel 3 I believe.
Ghostsonplanets@reddit
WCL is also fully I18A, including the Celestial iGPU
JobInteresting4164@reddit
I thought the main compute tile for NVL is 18A. Some other tiles on TSMC.
Famous_Wolverine3203@reddit
This is good news for 18A. Dr Cutress also points out that N2’s SRAM HC cell clocks in at 4.2 Ghz at 1.05V compared to Intel’s HC SRAM cells which achieves 5.6Ghz (!) at 1.05V.
6950@reddit
And people were saying 18A was a mess that's a freaking 33% frequency increase vs N2 those will make some fast and fat caches
PainterRude1394@reddit
The Intel hit pieces and Intel bad narrative seem to have peaked.
Finally back to some rational discussion based on reality.
logosuwu@reddit
Funny how all the Intel bad posters (especially the two most prolific ones) are suddenly very quiet lmfao.
ModeEnvironmentalNod@reddit
There was a lot. I got DV'd hard for pointing out this Intel merger/breakup stupidity.
no_salty_no_jealousy@reddit
They all scared of getting downvoted and look like a clown here.
no_salty_no_jealousy@reddit
Unfortunately there are still many redditor in here spreading non sense BS about Intel, most of them are AMD stock owner too which is not surprising anymore.
Tiny-Sugar-8317@reddit
Intel stock was literally up 16% just yesterday on increased rumors of a breakup...
ACiD_80@reddit
It wasnt becuae of the breakup rumors, thats just what nonsense media made of it...
Tiny-Sugar-8317@reddit
Yes it was. What do you think caused it instead?
ACiD_80@reddit
Simple, JD Vance's speech about made in the US and announcement of chip tariffs... Thats actually when the stock started to go up.
PainterRude1394@reddit
It was due to buyout, not breakup.
Maleficent-Salad3197@reddit
A potential buyout often raises the price. So Intel will get 5 more next year. That still leaves quite a few more years before they can have the output they need. Competition is good for everyone.
6950@reddit
Yes finally was getting sick of X,Y,Z company buying Intel
VitaminDee33@reddit
You seem confident that the relationship between yield results and financial viability of the foundry / fab seem fairly guaranteed? Got some proof that the end of this year will show a glimmer of hope in the earnings department?
6950@reddit
Cause it is if an X and Y process having the same PPA have different yield the one with the higher yield will be more financially viable from the view of buyer (customer in case Apple/NVDA/QCOM)
For example if a process X has higher Yield than Y even if X is slightly expensive. The X process will get more good dies out of a wafer than Y In the end you will get more out of X process financially as a customer.
For the process maker they have to produce less wafer for a given customer as well which saves cost for the maker and they can make for more customers.
Here is an example I have taken a 100mm2 chip and used different D0 to calculate the good die why would you prefer a Process with a process with higher D0 vs the lower D0 unless the cost difference between the wafer is substantial.
https://imgur.com/a/em8YesD
Famous_Wolverine3203@reddit
Very important to note that the frequency improvement is for the SRAM cell. Faster cache is always welcome but don’t confuse it with faster CPU clockspeeds.
ExtendedDeadline@reddit
It's not like we need fast clocks at this point, anywho. Faster cache would have outsized benefits.
Strazdas1@reddit
we do. We need 10 times the clocks. Unfortunately physics says no and we are stuck with multi-core designs.
Famous_Wolverine3203@reddit
It depends. Shaving of latency cycles does offer better performance but it isn’t always linear for every workload. Whereas general clock speed improvements are far more straightforward.
ExtendedDeadline@reddit
For sure, but clock speeds are the antithesis of power consumption. The future is not to push to higher and higher clocks and it hasn't been since Pentium 4!
Famous_Wolverine3203@reddit
I agree but faster cache clock speeds consume more power too though?
ExtendedDeadline@reddit
Clock stability for the CPU tends to scale with voltage. Power scales with the square of voltage. Voltage goes higher quickly in the "very high clock" regime for the CPU. It won't move meaningfully by comparison for cache. Higher cache speeds will consumer more power, but the power hit won't be as bad as trying to push the CPU to new and uncharted clock speeds.
Strazdas1@reddit
well he did say "fast and fat caches", not fast CPU.
Tiny-Sugar-8317@reddit
To be fair most negative stories about 18A were related to yields not performance. It's always been assumed to have good performance based on GAAFET and BSPD, but that increased complexity was rumored to come with poor yields.
advester@reddit
Not hard to believe that switching to GAA is good for SRAM design. The surprise is Synopsis claiming the same density, but with 3nm. And how are three different companies somehow getting the same density now? Sounds like collusion.
ModeEnvironmentalNod@reddit
Could be process engineering bottleneck. Might only be one way to do it, resulting in the same result. Refer to the perfected process for making paperclips for an example.
Famous_Wolverine3203@reddit
The SRAM lobby man! They’ve got their greedy hands on everything😶
theQuandary@reddit
Has it been a disadvantage or has Intel simply never had a use for something that dense/slow?
Famous_Wolverine3203@reddit
Unlikely to be the case since AMD always used HD SRAM cells for their CPUs. Not sure why Intel would say no to denser SRAM cells.
Strazdas1@reddit
Intel used HP cells for CPUs. HD cells only used in igpus.
Vushivushi@reddit
Should note that TSMC does it at 25C whereas Intel didn't disclose temp.
Famous_Wolverine3203@reddit
I assumed it was industry standard to measure at that temp?
Tiny-Sugar-8317@reddit
Intel 4 is a FinFET technology whereas 18A is a GAAFET. Different technology explains increases density.
anival024@reddit
SRAM is one of the simplest thing to tile. The fact that Intel is now claiming to be at parity is pretty meaningless.
Until Intel has competitive products you can buy (not "this year" or "on schedule", but "purchase now"), all this does is underscore how woefully behind they've been for so long.
Adromedae@reddit
#ShitRedditSays...
jaaval@reddit
I don't think it is a problem to place six transistors densely, it is a problem to make that small cell work fast and reliably with all the rc issues and also not leak like mad. And you need to size the transistors carefully as the sram cell needs some transistors to be bigger than others and that causes reliability issues when you try to make it all very small.
You have to ask some actual silicon design engineer what exactly the current issue is with sram but they all seem to have real trouble making it smaller.
Famous_Wolverine3203@reddit
I wonder why SRAM scaling is basically dead if it’s so simple to achieve.
They’re at parity with N2’s SRAM. Meaning they caught up to TSMC’s node that will show up after 18A products launch. And they’re not just at parity. They’re straight up better achieving 33% higher clock speeds on their SRAM cells.
Thats an entirely different matter altogether.. we’re comparing nodes here. Not products.
No-Waltz-5804@reddit
If you believe Intel's claim they wouldn't need a US government to do a "forced marriage" between TSMC and Intel, just look at any Taiwanese newspapers they said they will fight to the end
Famous_Wolverine3203@reddit
This is an ISSCC paper. You really can’t get away with lying a lot here. Also Intel’s woes can also be independent from 18A being decent.
WhoTheHeckKnowsWhy@reddit
yeah, the i9 285k still being so underwhelming despite being made on TSMC N3B shows their process lag from leading edge was grossly overblown.
It's definately there, big, but no where near as monumental as people thought; we now know Intel 7 was a very good 7/5nm tier process. That Intel's biggest issues are a deficient uArch.
Geddagod@reddit
It might have been a good, albeit extremely expensive, 7nm process, but I would struggle to see how one could have added the "/5nm" in there as well.
WhoTheHeckKnowsWhy@reddit
5nm is adjacent to 7nm, not 14/12nm or samsung 10/8nm close; but 7nm to 5nm isnt a clean leap like 28nm to 16/14nm, or 14/12nm to 7nm. Even 3nm couldnt carry Intel's uArch Woes out of the fog. Yes I understand this is a very complex problem I oversimplified.
But that 5nm is considered low yield doable with complex multi patterning on DUV, policy is banking on the 3nm barrier keeping mainland china at bay till they concoct their own EUV says everything us laymen can glean.
therewillbelateness@reddit
Is 2nm a clean leap from 3nm?
WhoTheHeckKnowsWhy@reddit
5nm is adjacent to 7nm, not 14/12nm or samsung 10/8nm close; but if 7nm to 5nm isnt clean leap like 28nm to 16/14nm, or 14/12nm to 7nm. Even 3nm couldnt carry Intel's uArch Woes out of the fog. Yes I understand this is a very complex problem I oversimplified.
But that 5nm is considered low yield doable with complex multi patterning on DUV and everyone is banking on the 3nm barrier keeping mainland china at bay till they concoct their own EUV says everything us laymen can glean.
WhoTheHeckKnowsWhy@reddit
5nm is adjacent to 7nm, not 14/12nm or even samsung 10/8nm close; but if 5nm isnt i clean leap like 28nm to 16/14nm, or 14/12nm to 7nm. Even 3nm couldnt carry Intel's uArch Woes out of the fog. Yes I understand this is a very complex problem I oversimplified. But that 5nm is considered doable on DUV says everything.
WhoTheHeckKnowsWhy@reddit
5nm is adjacent to 7nm, not 14/12nm or even samsung 10/8nm; but if 5nm was such a leap the 285k should have been a magic bullet on a 3nm class node over Intel 7 if 5nm was so flatly awesome over 7nm.
therewillbelateness@reddit
What was the oxidation issue?
Helpdesk_Guy@reddit
In what colorful universe equals a outsourced design, which somehow not even manages to outdo Intel's older Gens, TSMC being behind? The design of Arrow Lake itself is borked, not TSMC's process!
If it would be for TSMC's processes being the issue on Arrow Lake, how come other designs on even older TSMC-nodes outdo ARL? If anything, TSMC's N3 with Arrow Lake could eventually account for clockability.
Also, even the virtually world's best process can't help that much in giving a flawed Core- and design-assembly any greater leg-up.
If the design is stellar, it performs even on mediocre process-technology. If the design itself is borked like ARL, not even the best process can't help it.
Geddagod@reddit
You can compare it to MTL-H, which has an even more borked design (SOC wise) than ARL-H, and the perf/watt of LNC is \~same or slightly higher than RWC on Intel 4, when measuring core only power.
Still would suggest N3B is better considering LNC is a tock core, but not by the margin that was expected.
I will say though, I think Intel just borked their implementation of LNC on ARL vs LNL, since LNC on LNL has a slightly different physical design, and the curve for LNC on LNL is a good bit better.
This is measuring core power only, in subtests where the entire data set mostly fits into the core private caches, so I wouldn't see what other factors could influence the curve. This would indicate N3B is \~15-25% better than Intel 4 (and like 2x the perf/watt at Vmin).
Because Intel's designs are worse?
What?
Swaggerlilyjohnson@reddit
18a could be good and they could still be screwed. They could have yield issues or even if they have good yield companies may not want to work with Intel because they are unproven or more difficult to work with.
There could be lots of problems or it could even be a case of Intel board members having connections and preferring a risk free buyout so they pressure the administration to make it happen even though they think 18a will be successful.
When you're working with companies this large,governments and even geopolitics there can be a lot going on that isn't public.
Personally I am very confused at Intels state. More recently we have had more prominent people not connected to Intel and this ISSCC paper imply pretty good things about 18a.
Yet at the same time Pat was fired so I struggle to see how it could be going well. I lean towards either 18a production costs are higher than they would like even though it's a solid process or they were just done with all the design problems and the staggering r&d costs in foundry and GPU.
steve09089@reddit
I think Pat getting fired was most likely due to making a deal to get subsidies in exchange for not allowing the spin off of Intel’s fabs.
That probably pissed off investors who see the fabs as dead weight, or at minimum wanted an exit strategy in case shit hits the fan, which such a deal wouldn’t allow.
nyrangerfan1@reddit
Someone explain this to me in English.
Famous_Wolverine3203@reddit
The CPU cache (like L1, L2, L3) is what is being talked about here. Its the stuff that stores your instructions before your CPU executes then.
SRAM is the building block of CPU cache. So if the SRAM is more dense, you can put more CPU cache on a chip making it faster and more efficient.
Intel Foundry and TSMC now have the same SRAM density. Which didn’t use to be the case as TSMC was significantly ahead in that department. It seems Intel has finally caught up.
TheBCWonder@reddit
I still don’t get why SRAM is different from DRAM
DoctarSwag@reddit
SRAM = each cell made up of a bunch of transistors. DRAM = each cell made up of a capacitor plus a transistor. SRAM is usually faster and more easily made with the same process used for CPUs/GPUs, while DRAM is usually more dense. Thus SRAM is better suited for caches which need to be really fast and close to the CPU/GPU, while DRAM is better suited for main memory where you want high density but don't need it to be as fast
TheBCWonder@reddit
Interesting, my CE professor skipped over DRAM, so I kinda assumed all memory is just transistor circuits
Maleficent-Salad3197@reddit
They have a single machine. You must be kidding. Please put a /s behind your comment.
Ghostsonplanets@reddit
They have 2. And on their way to have the third installed. Regardless, i18A doesn't use High-NA EUV. That's for i14A in 27.
Strazdas1@reddit
What? 18A is not on high-EU machines. And they have more than one of those now. Its for 14A.
Maleficent-Salad3197@reddit
Caught up? Maybe in one fab in one unit. I think it's their fab in OR. TSMC has multiple units running at full capacity and Intel has to wait in line for any more from ASML.
Famous_Wolverine3203@reddit
Products on 18A are slated for this year. Namely a high margin server product (Clearwater Forest) and Panther Lake. You’re unlikely to see N2 products till Apple adopts it in Q3/Q4 2026.
Tiny-Sugar-8317@reddit
Let's be real; Intel will probably paper launch one 18A product in December. You won't actually see any 18A volume until 2026.
Famous_Wolverine3203@reddit
No, CWF is on track for Q3/Q4 2025 after which PTL comes in Dec 25 probably. But Intel only lies about product launches a year or two before launch. They’re usually honest if the product launch is within 2/3 Quarters.
Due_Calligrapher_800@reddit
CWF was pushed back to “H1 2026” due to issues with their Foveros direct 3D packaging
Famous_Wolverine3203@reddit
Source?
Due_Calligrapher_800@reddit
MJ Holthaus, verbal statement, in the Q4 earnings call. She said something along the line of 18A being healthy but complexities with advanced packaging for CWF will result in a delay to market to H1 2026 to give them time to figure out the packaging issue
smp2005throwaway@reddit
Hmm, Intel just delayed Clearwater Forest to 2026 (latest earnings). I think it was packaging issues.
I'm more worried about delays at Fab 52 and 62 (i.e. capacity issues); they kind of need to hit the ground running to sell enough PTL for people to care.
Tiny-Sugar-8317@reddit
Well, they certainly weren't honest when Pat was around. Maybe they've changed now, but trust has to be earned. I'm willing to bet money you won't be able to buy an 18A part for at least 9 months.
Famous_Wolverine3203@reddit
Well, ofc not, I can’t afford a 20k USD server part now can I?
Tiny-Sugar-8317@reddit
That's a whole separate issue, lol.
nyrangerfan1@reddit
So Pat's bet paid off?
Brilliant-Depth6010@reddit
Not until we know the density of logic. And until whether we know if Intel's foundries can become customer focused rather than Intel focused. Until then it is still just all talk.
III-V@reddit
We don't know yet. We will have to see if it's on-time or late. It also depends on whether they can score any customers, although I believe they won't have a ton of capacity.
Famous_Wolverine3203@reddit
In one aspect of the chip. SRAM density and performance is a crucial aspect of a process node, but it is in the end, one aspect of it.
There’s others like logic density, PnP etc which where also a few aspects where Intel lagged behind but we don’t know to which extent, Intel has caught up.
Imnotabot4reelz@reddit
The main thing Intel was thought to lag behind TSMC this coming gen was going to be SRAM scaling. This is basically when you are trying to make memory. The fact that it is identical means Intel's chips will be much better for things like Cache, which increasingly takes up more and more of chip space.
Overall, it just means Intel may in fact beat TSMC straight out this generation, whereas before it was really only possible to beat them in everything but Sram. Huge news for intel.
Famous_Wolverine3203@reddit
I’d be a bit cautious before exclaiming that. SRAM is in the end only one aspect of a process node. There’s so much more like logic density, performance and efficiency that we don’t know about. 18A is the closest Intel has ever been since 2018, but I’d keep my expectations a bit more realistic if I were you.
eding42@reddit
At the minimum it doesn’t look like 18a is the N3 competitor like a lot of Intel’s detractors were saying.
Famous_Wolverine3203@reddit
Without power and performance data, it is hard to say anything.
Strazdas1@reddit
Yes but if we know that 1 part of the chip is doing well and arguably better than expected and 2 we dont have information on the rest of the chip, assumption that the chip is bad is certainly premature.
eding42@reddit
True but we can hope...
theQuandary@reddit
Wasn't there an article a week or so ago claiming 18A is more efficient with high-performance transistors?
Geddagod@reddit
That is definitely not true. The main thing Intel was thought to lag behind TSMC this coming gen was high density logic density.
Quoting the Jones' 18A article from a couple days ago:
This was always thought to be the biggest problem. And even before anything about 18A SRAM was shown, the discourse around SRAM in general was that scaling was slowing down, meaning Intel would inherently have an easier time catching up there.
Before it was really only possible (or it was conjectured) that Intel may be able to beat out TSMC in high performance, high voltage CPU cores. This new news does not change that opinion much, IMO.
tset_oitar@reddit
TSMC N2 HD logic should be roughly 255Mt/mm2, 1.2x over the highest density N3(215Mt/mm2, 143H). Jones used the single fin N3 configuration(117H or 262Mt/mm2, which isn't even advertised by TSMC btw) to obtain the 315 number for N2. Highest density observed on high volume N3E devices was 215Mtr/mm2, in the iGP portion of mobile socs afaik.
Overall, yes N2 leads 18A in logic density, but not by such a large margin. Also density can change depending on PnP, even mobile iPhone soc P cores are making use of higher performance logic libraries
Geddagod@reddit
Considering Jones' earlier comments about 18A hd density, I'm assuming he is using the densest possible configuration on both nodes, even if they don't end up being used in products.
Additionally, given Intel's own choices in using external nodes for their compute tile (cough NVL cough), I'm not convinced that Intel sees even 18A-P as the best node even for high performance CPUs.
Dexterus@reddit
NVL is supposed to be half/half, no? Though I would guess N2 for desktop S/laptop HX, 18A rest.
Raikaru@reddit
Isn’t Panther Lake literally using 18A fully?
Geddagod@reddit
I was talking about Nova Lake. Intel confirmed they are going external for the compute tile for NVL along with internal. The split would likely be 18A-P and TSMC N2. And I would imagine there's very little point of Intel going external for the compute tile unless it was worth it, paying the extra cost.
Famous_Wolverine3203@reddit
GPU tile is N3E.
Famous_Wolverine3203@reddit
This is weird since Jones’s own article now states that 18A achieves 238Mt/mm2 which is far higher than any N5 product to date. TSMC didn’t even advertise a single fin N5 lib so even that excuse is void.
Famous_Wolverine3203@reddit
I was under the impression that Apple does use the single fin config in some parts of their SoC?
tset_oitar@reddit
One of those soc teardown Twitter accounts only found Finflex 2+1 mixed library
Famous_Wolverine3203@reddit
If you could find a link, that would be much appreciated. Thank you!
So N2’s standard HD lib is 255 Mt/mm2 compared to 18A’s 238 Mt/mm2 for their HD cell I think. Thats what a 7% density advantage?
Geddagod@reddit
Here
Famous_Wolverine3203@reddit
Thank you. This is unexpected. I didn’t know there were vtubers with anime cat avatars that covered the density of transistor between different process nodes. But I’m mildly glad.😂.
Geddagod@reddit
LOL
Imnotabot4reelz@reddit
Do you have a link to this? Can't find it on google.
Geddagod@reddit
I'm saying that Intel 18A's HD logic density was always thought to be further behind TSMC than their SRAM density was.
No, because we don't know what configuration Jones's 18A logic density approximation is either. The quoted 18A density could easily be similarly maxed out density configs.
Intel's own products historically have not hit their quoted max density either.
Famous_Wolverine3203@reddit
Intel doesn’t have a single fin variant on any of their nodes till now so it’s pretty much impossible that he was using a theoretical single fin configuration to compare 18A and N2.
The above comment explained it best.
Geddagod@reddit
Create a free account with Techinsights and check out this article.
Imnotabot4reelz@reddit
Sorry I edited my post I ended up finding it.
Seems as I said above in the edited post, that those numbers are comparing ONLY TSMC's standard cells, to Intel's mixture of cells, so doesn't seem all that useful.
Geddagod@reddit
It's calm I lowkey was tweaking at first lol but I'll respond to the edited comment.
Famous_Wolverine3203@reddit
While this is a good point, it should be noted that Intel is achieving much higher clock speeds (33% higher) on their HC SRAM cell compared to TSMC’s HC cell. I’m assuming this means less latency cycles?
makistsa@reddit
Intel even at their best node(intel 3) was behind tsmc in cache density. 18a has the same density as tsmc's upcoming N2 and may clock higher at the same volts
Famous_Wolverine3203@reddit
The HC cell specifically. We don’t know about the HD cell.
eding42@reddit
Ehhh the HD cell isn’t particular relevant for Intel’s use cases
Famous_Wolverine3203@reddit
Intel uses HD SRAM cells in a lot of their products.
juGGaKNot4@reddit
In english, it doesn't mean anything.
I've been reading on reddit how intels nodes are better than tsmc's for the past 5 years.
Every time the products that launch from those nodes are delayed for years, not competitive and don't launch in volume ( probably yeald issues ).
So its PR.
soggybiscuit93@reddit
no you haven't
Objective-Note-8095@reddit
Wake me when there's an Arc.GPU.based off 18A
steve09089@reddit
Celestial dGPUs are rumoured to be based on 18A, but that remains to be seen whether it actually comes out. .
Famous_Wolverine3203@reddit
Celestial dGPUs are cancelled to my knowledge.
ACiD_80@reddit
Cancelled order for TSMC probably.
ThankGodImBipolar@reddit
That’s what MLID has been claiming. This is the rumor being referenced above.
ACiD_80@reddit
people still listen to that troll?!
Famous_Wolverine3203@reddit
Even a broken clock is right twice a day in mLID’s case. There’s very little chance Celestial dGPUs see the light of day. Shame too since the architecture is apparently exemplary (1.6x LNL perf).
protos9321@reddit
How did you get PTL as 1.6x LNL?
PTL (12Xe) is 50% larger than LNL (8Xe) so the ipc and clock uplift together is less than 10%? That doesn't make any sense. Are they reducing LNL's clock which was already only 2GHz by a significant portion?
Famous_Wolverine3203@reddit
They somehow fit 192 EUs in there.
Ghostsonplanets@reddit
96EUs
protos9321@reddit
So is it the IPC that you are referring to being the 60% increase? Xe2 was a 70% IPC increase over Alchemist. The over GPU is larger as its 12Xe Core vs 8Xe core on LNL. So would the perf increase then translate to a 246% perf increase over LNL at the same clock (2GHz)?
Famous_Wolverine3203@reddit
Not exactly. They fit more 3x more EUs without increasing area significantly. You can call it an IPC regression? in favour of fitting more cores in the same area.
This is a huge achievement since the nodes are very similar (N3E vs N3B). I’m unsure as to how you can calculate IPC from that.
I’m unaware of the exact details, but the a very reliable source has indicated that general performance estimates are 1.6x over LNL’s iGPU.
ThankGodImBipolar@reddit
I’m not really a part of the “MLID is never right” train in the first place, so I’m not expecting Celestial dGPUs right now either. That’s just what’s being referenced, if I had to guess.
F9-0021@reddit
He's been claiming that Arc is canceled since before Alchemist released. He's not a reliable source, especially for Arc.
ThankGodImBipolar@reddit
He’s been claiming that Arc is effectively canceled. He claimed that the largest Battlemage die wouldn’t come out, which appears to be correct thus far.
soggybiscuit93@reddit
The nice part about using the term "effectively" is that he can retcon whatever he was trying to say to just be right.
I suppose RDNA4 is also "effectively" canceled too? large BMG doesn't need to launch. Even a single Celestial dGPU launch would prove him wrong. I'd even go so far as to argue that if Intel makes a large Strix-Halo style APU with Arc graphics, that proves him wrong too.
Ordinary-Depth-7313@reddit
That is a revised claim, he initially claimed it was completely canceled. He was wrong.
Strazdas1@reddit
Intel said otherwise just last week...
Traditional_Yak7654@reddit
They aren’t.
Famous_Wolverine3203@reddit
Nova Lake’s iGPU is apparently on 18A-P.
cyperalien@reddit
The SOC tile too is on 18AP.
Famous_Wolverine3203@reddit
Yes. I just pointed out the GPU side of things for the above person.
SlamedCards@reddit (OP)
Great thread by Dr Ian Cutress. Both TSMC and Intel are running test chips at 0.021 um^2 SRAM density (same as TSMC 3nm) . But can achieve 0.0175 um^2 depending on the tradeoffs a designer would want. Intel didn't advertise this in the headline paper so many people such as myself thought 18A lagged in SRAM density vs N2. Not the case. Lots of cool slides posted including the frequencies achieved by N2 and 18A for SRAM
NyanArthur@reddit
This is great but why is it called 18A
pianobench007@reddit
Number go down. Or add a plus. That's all.
For Nvidia it is number go up and stick to 4 digits.
NyanArthur@reddit
I know was just making a joke about that guy asking why 18A in the article
SiloTvHater@reddit
lmao this is a reference to the top comment about that guy isn't it?
NyanArthur@reddit
Yeah lol
Famous_Wolverine3203@reddit
It seems that they prefer to use the HP to show off results since it achieves the best case frequency figures compared to HD cell. It seems they expect designers to go for the HC cell than the 0.0175 um2 variant.
Strazdas1@reddit
Intel uses HP cells almost always. The only place HD is see is in the iGPU for modern chips.
Adromedae@reddit
It's more a case of some people in this sub making all sorts of extrapolations from data that Intel had never provided.
quarpronuet@reddit
there is no such thing as 0.0175um2 bitcell at all. that was just useless reverse calculation of macro density to bitcell density; from people who don't even understand the difference of bitcell size and macro density,
HD bitcell from both are 0.021um, and macro density varies by how to design and configure macros. usually longer BL/WL for higher density at lower speed. and the macro density presented are for the highest density macro.
Maleficent-Salad3197@reddit
Yes Im sure. If Intel hadn't cheaped out and waited to but in ASML could have delivered the same machines that TSMC has been using. Intel has simply waited to long. Those fab machines are very $$$ are made slowly and the wait in Queue is long.
grumble11@reddit
Intel basically has a one-year monopoly on High-NA machines for 14A - TSMC got some, but after intel did.
Helpdesk_Guy@reddit
Yes, the the whole volume of 2024 exclusively for Intel, yet these are just mere 5 machines…
Please don't buy into Intel's hype, their false marketing and inform yourself for once!
AFAIK Intel still has only a single (1) High-NA machine installed and running yet, while a second one gets currently adjusted (which takes months to +1yr) and getting a third delivered (takes 6–9 months); AMSL's Twinscan NXE:3800E.
Here's the link to it, if you care for some reading …
This machine just got delivered to Intel in March 2024, thus only a couple of months ago!
Said machine comes with a *theoretical* throughput of 220 Wafers/hr, if everything runs according to plan (which it never does). That's just 220 wafers/hour off a single EUVL High-NA-machine. As you already note, Intel has booked all five High-NA-machines of ASML manufactured in 2024.
TSMC has meanwhile acquired 84 (eighty-four!) EUVL-machines in 2022 alone, more than +100 in 2023.
Also, TSMC operated around ~10 EUVL-systems in parallel when starting their second 7nm-class yet the world's first EUVL-node N7+ in 2019 – TSMC's first 7nm-class node N7 was still exclusively DUVL-based, only N7+ had involved around 10 layers of EUVL-exposure as a world's first.
So that are just +180 EUV-machines at TSMC (yet low-NA EUVL-machines, like the AMSL Twinscan NXE:3600D and others), offering a max wafer-throughput of 120–160 Wafer/hr (old–newest-gen), which equals around 21,600 EUV-wafers/hour on a conservative estimate (180×120 wafer/hr) and 29,700 EUV-wafers/hour on the possible upper end (180 ×165 wafer/hr), when it's likely more around ~24,300 EUV-wafers/hour (180×~135 EUV-wafers/hr on average).
Now compare that to Intel's "huge" volume of Intel's at best 5 High-NA-machines;
That's just 5×220 wafer/hr, at best. Equaling 1,100 EUV-wafers/hour, theoretically.
… on a hypothetical number of theoretically already installed High-NA-machines, which isn't even the case.
Keep also in mind, that these figures of +180 low-NA EUVL-machines TSMC and others bought since 2022 are for sure already outdated and expanded in number. Intel's ain't. I'm sure you're smart enough to grasps the very implications of all this, and may finally able to see through all the smoke and mirror-games that Intel plays here…
tl;dr: Don't buy into the hype. Intel's EUVL (-High-NA) volume is not even a joke compared to anything TSMC.
animi0155@reddit
Your point is...? Intel is still going to have 5 High-NA scanners in D1X for R&D sooner before TSMC will in Hsinchu. So relatively speaking yeah, it's a reasonably large advantage. That's still a lead on getting the tools up and running and developing the process for them. It doesn't stop Intel from evaluating low-NA EUV multi-patterning either.
Comparing absolute low-NA EUV install base and theoretical output is irrelevant here? Like, no shit TSMC has way more of them? They have have way more fabs with more wafer volume. Intel doesn't have an EUV capacity problem nor is their installed fleet likely to be particularly outdated. They have the tools they need for the purposes they use them for.
Also the high-NA scanners are the EXE:5000 and EXE:5200. NXE:3800E is a low-NA scanner. If you're going to give out links for other people to read, you should make sure they're all correct.
Helpdesk_Guy@reddit
And your point is then? What does is matter (even if Intel would have had all 5 High-NA-machines up and running), when TSMC still outdoes them in raw through-put and volume using older Low-NA-machines?
Your point is virtually non-existing, as there's no real actual advantage in favor of Intel here.
No. There's none whatsoever advantage – There wouldn't even one, if both TSMC and Intel would hypothetically start at the same time with Intel and their 5 High-NA machines vs TSMC and their load of hundreds of low-NA machines.
No … No offense here, but either you're rather unaware about the actual differences of High-NA EUVL vs Low-NA, or your really bought into the Intel-marketing way to hard to understand what's actually at stake here.
You pretend or at least make it sound, as if the difference in-between High-NA EUVL vs Low-NA would be night and day, when it's merely literally aperture-size/granularity and through-put really, simply put, of basically only fine-tine the same machines.
The difference really are a slightly evolutionary step instead of the revolutionary and quite fundamental one of DUVL vs EUVL.
Besides, high-NA EUV single-patterning costs significantly more than double-patterning using existing low-NA machines for upcoming technology nodes including 1.4nm/14A! Furthermore, multi-patterning low-NA EUV is still capable of finer pitch-features than high-NA! – The source here is ASML-engineer Jeff Koch, having recently left ASML.
So if anything, even if Intel has now some expertise on high-NA (or at least successfully pretends so), the actual handling-differences between both High-NA machines and Low-NA machines are really not that different anyway and actually quite minor to virtually the same, as compared to the gross difference of EUVL vs DUVL-machines – TSMC still outpaces Intel in that regard because of its way longer-lasting experience here.
So even if so, low-NA is way more expensive to manufacture anyway – It will come to financially haunt Intel even more than its already is!
Yup, my bad! That was of course the low-NA machine TSMC/Samsung/Micron operate since.
animi0155@reddit
You don't seem to understand that I'm only talking about R&D. At some point HNA has a cost advantage over double patterned EUV and getting a head start on making the process economics work might pay off. The machine is only part of the solution. Photoresists (and track tooling), masks, pellicles, all of these need to be developed and optimized for HNA EUV, and having an actual tool in the fab to develop on is quite important. And again, you don't have to abandon low-NA multipatterning. You can develop both in parallel and insert whatever is most economical at the time. Intel certainly has the capacity to develop 14A and beyond with low-NA double patterning and high-NA direct print.
Semianalysis also put out an article (also with contribution from Jeff Koch) that Intel was investigating DSA to potentially improve the economics of HNA to make it substantially more viable. If they can develop it to intercept 14A, that's an advantage.
You don't know what my background is. That kind of assumption and language is disrespectful no matter what you say.
No-Waltz-5804@reddit
It's like a Samsung saying they had GAA and can producing two 2nm three years ahead of TSMC ... Intel's case I put a big question mark, because it has been seen this ever since 14nm, 10nm, and so far as it has not been produced anything below 7nm even 7nm they are in trouble trial production, currently still in the limited production. Let's be honest face effect be honest with ourselves ... Jump from 7mm to 2 mm that's like two or three generations without trial and error ... Yes Samsung claimed they can produce 2nm years ago what about their production quality, below 20% of satisfaction rate
ACiD_80@reddit
Intel's Xeon6 CPU's are made using intel3
Famous_Wolverine3203@reddit
Intel actually has products releasing this year. We’ll know soon enough.
Helpdesk_Guy@reddit
The keyword is *scheduled to be released … And we all know by now how that usually turns out with Intel.
Intel itself has factually ~~evolved~~ adapted the Linux-world's "rolling release"-methodology with their road-maps.
Geddagod@reddit
Very interesting. I'm not sure how cross-comparable the two shmoo plots are, but pretty bullish for 18A either way.
I wonder if this is why PTL's P-core is rumored to have shrunk in core area vs LNC. Comparable logic density, but perhaps denser caches are the reason for the shrink?
Very excited to see the rest of the slides in a couple of weeks, and very much looking forward to the eventual PTL die shot and perf/watt testing.
Famous_Wolverine3203@reddit
18A’s HD cells are around 10% denser in logic compared to N3E. That probably helps a bit too.
tset_oitar@reddit
Intel never uses hd logic though, BMG G21 on TSMC N5 somehow has Xtor density of an N6 device
Adromedae@reddit
Huh? What makes you think Intel doesn't use HD cells?
ResponsibleJudge3172@reddit
They really don't. Last time they used a device not inline with HP density was the original 10nm laptop chips
Adromedae@reddit
They really do. Designs use mixed-libraries all the time.
I have no idea why you think intel is an exception here.
Geddagod@reddit
They use HD logic in their iGPUs.
Famous_Wolverine3203@reddit
Yes, LNC uses N3B HC I think? So 18A’s HC cells should be quite a bit denser as well.
Intel’s HC cells also have been historically competitive in density with TSMC’s HC cells.
Brilliant-Depth6010@reddit
Yeah, but SRAM has scaling problems with advancing process nodes, right? Give us the transistor density of logic, or don't both to tell us about it.
martylardy@reddit
Dang...Intel's 1.8 is starting to look mighty tasty...
U3011@reddit
Good news and looking forward to products now.
Famous_Wolverine3203@reddit
While this is a good point, it should be noted that Intel is achieving much higher clock speeds (38% higher) on their HC SRAM cell compared to TSMC’s HC cell. I’m assuming this means less latency cycles?