Are we likely to see Zen5 refresh before Zen6 ?
Posted by Trey_An7722@reddit | hardware | View on Reddit | 32 comments
I see massive increase in CUDIMM presence, with ever higher frequencies. We are now at 9600MHz for top models, but that's likely to increase further. And then there is LP/CAMM2 and MRDIMM.
All of them used by Intel, but so far ignored by the AMD. Given that they offer advanteges for many-core and APU systems at basically no significant extra cost, are we likely to see AMD refresh that supports them ?
Would new IMC be enough or does IF have to be reworked/widened/speeded up to support it ?
How likely is that upcoming 9xxxx APUS are the first line with improved I/O chiplet, just like the 8xxx has improved IMC from 7xxxx ? 🙄
ET3D@reddit
It's unlikely. The is no real incentive for AMD to implement this, as it already wins convincingly in games over Intel (with X3D) when using 6000 RAM. So better performance, cheaper RAM, win-win.
capybooya@reddit
Yep, I see lots of wishful thinking in various places, but it makes absolutely no sense for them to take on additional costs and complexity. They have a cycle, which they've executed quite steadily on for years as well.
RetdThx2AMD@reddit
Beyond no incentive there is negative incentive. Any uplift that can come from an improved I/O die is a performance gain that Zen 6 would have over Zen 5 by default. Given all the bad press they got from Zen 5% they would be inclined to ensure that Zen 6 is a big uplift generation. Making a Zen 5 refresh both cuts into Zen 6 sales and diminishes its mind share.
SignalButterscotch73@reddit
An improved I/O die would probably help Zen5's performance since it appears to be bandwidth starved going by the 9800x3D's productivity improvement vs the 9700x.
If it's something they can do easily and cheaply then a refresh with a new I/O wouldn't surprise me.
I doubt it will happen though. If they move to a new socket with zen6 them more x3D chips are the most likely way they'll keep zen5 and AM5 alive, especially if they can get base zen6 to be competitive with zen5x3d.
Similar to what they're doing now with zen3x3d and AM4.
Without a new socket then a refresh wouldn't make sense, they'll just keep doing as they are now. Older gen acting as the new low end until supplies run out.
Firefox72@reddit
I doubt they will.
SignalButterscotch73@reddit
I doubt it too, but that commitment doesn't specify that anything beyond zen5 will be on AM5.
AMD will get crucified in the press if they do change socket for zen6 but the constant zen3 releases on AM4 and claim that it's still supported makes me fear slightly that they haven't decided yet if zen6 is going to be on AM5.
Trey_An7722@reddit (OP)
Why would they need a new socket for CUDIMM, LPCAMM2 and MRDIMM support ? They all use existing signalling. Intel didn't need a new socket for any of this... 🙄
SignalButterscotch73@reddit
AMD like to do things that way, they didn't need AM5 for DDR5 but having a mix of DDR4 and DDR5 AM4 motherboards would be far more cluttered than having a clean split between AM4 can do this and AM5 can do that.
Trey_An7722@reddit (OP)
Apples <--> oranges. This isn't like DDR4->5 jump.
There one had to make certain sacrifices to make a jump. DDR5 was designed with newer silicon in mind, so signalling thresholds and power voltages etc were optimized for that.
All of that stays teh same here.
SignalButterscotch73@reddit
It's about segregation not the tech itself. AMD like to segregate via socket rather that chipset or RAM.
steinfg@reddit
About Zen 5 refresh, there are some facts to consider.
IO die will definitely be updated for Zen 6. There's a good chance we'll see CUDIMM support there. This IO die reportedly uses new IFOP, based on RDL, like MCDs on RX 7000 GPUs, and like CCD on Strix Halo. It may be possible to put Zen 5 CCD from Strix Halo on a new Zen 6 IO die (if it's compatible), but would it make sense financially?
I think it only makes sense if the Zen 6 IO die will be ready a whole year before Zen 6. If it comes out like 6 months before Zen 6, it's not worth it to refresh.
So accounting for all that, I think it's gonna bevery unlikely.
About Zen 5 APUs: No. Those won't support CUDIMM. Ryzen 300 series (Zen 5 APUs) have max DDR5 speed of 5600 (LPDDR5 is a different protocol), probably reusing memory controller from Zen 4 APUs, since they're all on one node. When porting to desktop, it wouldn't make sense to add CUDIMM support to what's supposed to be an office / light gaming machine.
Trey_An7722@reddit (OP)
I don't see why would an I/O update present such a massive job. AMD does these chplets all the time. I/O die for any EPYC is MASSIVE compared to this. And yet they do new models there when/where they need them.
Samy with APUs. If this was so massive job, why is 8xxxx done in monolitic form ? Why wiuldn'tthey go for smaller chiplets, that are cheaper, don't need extra R&D as they could use what they had for 7xxx series etc ?
Something here doesn't add up for me.
Only fly in the ointment might be speed of existing IF, but even as it is, it could use extra bandwidth, even if it has to spread it between the chiplets.
steinfg@reddit
>I don't see why would an I/O update present such a massive job
Because Zen 6 IO die may use a different protocol compared to Zen 5 / Zen 4 IO die. It may not be possible to use the new IO die with zen4/zen5 (i'm just guessing)
>And yet they do new models there when/where they need them
Turin actually makes them ungodly amounts of money, up to $15K per chip. So they can make a new IO die for Zen 5. But talking about server, they still reuse IO dies there all the time. Sienna, Bergamo, Genoa, Stormpeak (so basically any Zen 4 or Zen 4c based server chip), all of them use the same IO die.
Trey_An7722@reddit (OP)
So, they don't have the resouces to reimplement an IMC block in the I/O chiplet, but they had the resources to reimplement WHOLE ZEN4 APU (ZEN4 cores AND whole I/C, including IMC) as a monolith die ? And do all that for a preipheral low-power office-use niche ?
As I said, something doesn't compute in that theory, at least for me.
steinfg@reddit
Yeah, cause they're not getting into laptop market with a desktop chip. Return on investment is massive. Return on investment of updating IMC is negative 🤣 couple million dollars for new masks, all for 100 nerds from the whole planet to buy it with cudimm memory, all to lose to RX 6600 anyways.
Trey_An7722@reddit (OP)
So why did they do monolitic desktop APUs 8600G/8700G then ? 🙄
steinfg@reddit
Again. desktop IO die can't be used to make laptop chip. So AMD has to make at least one zen4 chip for laptops from scratch. Now the question is - will it be monolithic, or chiplet. AMD has to spend money on masks for at least one chip regardless of choice. It makes more sense to go with monolithic in this case, probably because of higher power use when using chiplets.
Trey_An7722@reddit (OP)
I wasn't talking about mobile but desktop. By presented theories these monolithic parts (8xxxG) shouldn't exist.
steinfg@reddit
8000G desktop series is literally the same chip as 8000 series laptop chip, zero modifications. AMD is not spending any additional money on masks / chip development there. They just grab 8000 series laptop chip, and instead of putting it on FP8 BGA substrate for laptops, they put it on the AM5 substrate.
It's the same with 5000G and 4000G and 3000G and 2000G
steinfg@reddit
8000G is literally the same chip that's in 8000 laptop, zero modifications.
Numerlor@reddit
i.e. the market they still haven't penetrated properly and is definitely a big focus. I'm aslo pretty sure the design is mostly the same on the monolithic die, things are still going over the fabric
Irisena@reddit
Usually laptops are so space constrained that monolithic chips are preferred due to its simplicity and low footprint.
Because EPYC needs like 12 channels of DDR phy and stupid amount of cores that IO die needs to connect and feed.
T1beriu@reddit
It's more about the efficiency. Chiplets suffer a lot at idle in this front.
Trey_An7722@reddit (OP)
Why not ? Desktip APU on AM5 has much higher available TDP ceiling. Higher it can reach, more market share ait can gain as more of the users can find it to fit their needs.
Which is a big plus especially now that GPUs are so overpriced due to AI and Bitcoin craze.
steinfg@reddit
Look at the price of a Strix Point Ryzen 370 laptop ($1300+). Look at the price of a Ryzen 370 mini pc ($900+). Look at the price of RX 6600, which is 2x more powerful AT LEAST (and for just $200).
Are you actually deluding yourself? 8700G is already a niche product, most people buy 8600G / 5600G.
Trey_An7722@reddit (OP)
It's painful to watch AMD dragging its feet with this, given that with its many cores and strong iGPU they are the ones to profit the most of it. 🙄
b3081a@reddit
CUDIMM is basically DOA for most consumers in current situation, for at least 2 years.
The only platform that properly supports it is a giant mess that's unlikely gonna outsell their own last gen chips, and even on that platform it only helps specific workloads that absolutely prioritizes bandwidth, and only benefits when the user is extremely unwilling to OC and would like to stick to JEDEC 6400 speed. With XMP you can get to not-bad performance (8000+) w/ cheaper UDIMMs on ARL as well.
Trey_An7722@reddit (OP)
All of which would fit IDEALLY for bandwidth-starved 9950X as well incoming APUs.
From-UoM@reddit
There were roadmaps of Zen 5 on TSMC 3nm.
But with intel struggling I don't see client cpus launching. Maybe server oness
TheeAaron@reddit
Does Gen 5 support CuDimm?
Trey_An7722@reddit (OP)
In HW no. All it has is BIOS support (8at best) for "limp mode" - it basically bypasses CLK regen. And it sets stock frequencies.
Trey_An7722@reddit (OP)
Simple back-of-the-napkin projection:
So, fast single rank LP/CAMM CUDIMM combo should be able to reach 13000-1400MHz. That's more than TWICE of current golden combo for Zen5 (6000-6400 MHz 1:1 for the lucky ones). So theoretically even current 9xxxx IMC should be able to do it at 1:2 and suffer minimal syncronisation delays since memory clock is exactly aat 2:1.
Why woudn't AMD at least add CUDIMM support for clock regeneration ? 🙄