Putting together 9800x3d system this weekend, just want sanity check on NVME placement in Aorus Master x670e

Posted by Vizkos@reddit | buildapc | View on Reddit | 2 comments

Just want to verify my understanding around the implications of NVME placement on the mobo

Pics of the diagrams from the manual:

https://i.imgur.com/wGqrJj7.png

https://i.imgur.com/6OKXFSF.png

Link to manual: https://download.gigabyte.com/FileList/Manual/mb_manual_x670e-aorus-master_1103_e.pdf?v=54c13ebeec9f5a46ebba720fb5759a45

Assuming I am understanding correctly, the manual states that I can an NVME drive in every slot, if I wanted to (2x pcie 5 and 2x pcie 4), and not gimp my GPU at all, is this correct?

Assuming the above is correct, the obvious "best" configuration for 3x nvmes would be M2A_CPU, M2B_CPU, and M2C_SB?

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lichtspieler@reddit

Your Gigabyte X670E MASTER got for each of the 4 M.2 a 4x bus and the 16x GPU lanes are not bifurcated if you use the CPU_M.2 with PCIE 5.0.

I was considering the Gigabyte MASTER board aswell (got multiple for Intel and AMD systems), but I went for AM5 with the ASUS (X670E-F) because ASUS included tuned EXPO timings for my 64GB RAM kit:

https://imgur.com/2q2g8GO
4x M.2 (PCIE 4.0)
4x SATA
16x GPU (PCIE 5.0)

And yes you want to populate the CPU_M.2 first, since those are directly connected to the CPU, the PCH M.2 still share the 4x PCIE 5.0 lanes with everything else that is provided by the PCH.

A single PCIE 4.0 NVMe will just gain a bit more latency over the PCH, but 2x NVMe's will show bandwith limitation over the PCH during peak utilsation.

Since you looked up the mainboard manual and PCIE bifurcation for your board, it is normal that you start to question build on social media and youtube. :D

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antiDST@reddit

Assuming I am understanding correctly, the manual states that I can an NVME drive in every slot, if I wanted to (2x pcie 5 and 2x pcie 4), and not gimp my GPU at all, is this correct?

That is correct. The 9800X3D provides a total of 28 PCIe 5.0 lanes, 24 which are usable: 16 for the graphics card, 4 for M2A_CPU, and 4 for M2B_CPU. The 4 unusable lanes are reserved for communication with the closer chipset.

Assuming the above is correct, the obvious "best" configuration for 3x nvmes would be M2A_CPU, M2B_CPU, and M2C_SB?

I would say so.

I see tons of builds where people avoid the CPU slots, preferring the chipset slots, for reasons I don't get, which makes me question my entire understanding of how I interpret mobo manuals. For example, one build with this same mobo, they installed their single NVME in M2B_CPU, despite it seemingly offering the same as M2A_CPU (and requiring they remove their GPU if it has issues)...

I've seen pictures of builds like that, but usually it's because they assume that all the slots are the same and don't know any better. Some people also don't like the look of their M.2 drive, so depending on how the motherboard is laid out, will try to hide it behind the video card's cooler for aesthetic reasons, even if it means having to take it out to get to the drive if necessary.

Placing an SSD in the M2C_SB slot adds a propagation delay since they have to pass through the southbridge chipset. In the case of M2D_SB, it has to pass through 2 chipsets, so the delay is even worse.