I get my figures from having been in industry and having been part of the managing team for several architectures.

Are those figures proprietary and not in the public domain? I'm not necessarily doubting you here, I'm certainly aware that my knowledge of DEC's inner workings is that of an outsider, I'm just curious if I can add to my knowledge.

A lot of people on these subs musing about CPUs really are not aware about the figures involving in developing a competitive high performance design.

I don't really get that impression. People here mainly focus on the technology.

They were architectures with markets not growing fast enough to make the ever increasing development costs worth it. Especially when competitors started to pass them by in performance, for a fraction of the cost.

The problem wasn't so much the TAM as it was with the fact that the RISC vendors all competed with each other instead of with x86. The Microprocessor Report noted this phenomena back then. Sun even went around killing off SPARC clone makers during the first half of the 1990s at the same time they were promoting SPARC as an open platform suitable for cloning!

MIPS almost went under trying to get their out-of-order arch and they had to be rescued by SGI, and both orgs never really recovered.

MIPS wasn't the sole factor. SGI went on a wild adventure in the mid-1990s with the acquisition of Cray Research. They spent hundreds of millions on that, and many millions more trying to combine aspects of both Cray and SGI systems. And this is just the money, to say nothing of the time and effort.

SUN literally was never able to push an out-of-order design out of the door and basically they died trying to make Rock (Only Fujitsu was able to execute in that regard when it came to SPARC).

Sun's record of processor development didn't inspire confidence for reasons other than superscalar execution and dynamic instruction scheduling. Almost every single one of their processors suffered from severe problems; only the UltraSPARC I and MicroSPARCs (a simple pipelined scalar design) did not.

The entire industry was well aware of these increasing costs as far back as the late 80s. When it was obvious that superscalar and out-of-order was going to be really expensive in terms of development.

Only relative to the microprocessors of the 1980s, when the state-of-art technology was pipelining. I dare say a significant portion of the "high" cost was due to the 1990s and early 2000s penchant for full-custom dynamic logic. IBM went with standard cells and spent the money on process technology instead, achieving a respectful lead in some aspects over everyone else (including AMD & Intel); SOI and low-k dielectrics, for example, were featured in IBM technologies a year or so before Intel and AMD got it (AMD actually did joint development with IBM in the late 1990s).

IBM had to leverage PPC and their mainframes to reuse as much as they can to still keep POWER a thing, but they are starting to think twice nowadays.

From what I've seen, that only started to happen in the mid-2000s when the POWER6 and z196 (the model might be wrong) started sharing more low-level IP. In the 1990s POWER/PowerPC and mainframe microprocessors were very divergent in their design and designers. Little was shared beyond process technology, standard cells, and the design methodology/tools. Mainframe microprocessors didn't even get superscalar execution and dynamic instruction scheduling until 2003 with the z990 (the name might be wrong).

HP also saw that. Which is why they figured out they wouldn't go past PA-RISC 2.0 on their own, so they chose to partner with intel. For better or worse, they decided on PA 3.0 being a implicitly wide design (initially called PA-WIDE), that eventually became IA64.

That was more of a technology & fab issue I think. HP didn't want the expense of developing their own proprietary CMOS technology and the continual upgrading their fabs to chase smaller feature sizes. It should be noted they continued to design the first-generation Itanium (Merced) during the second half of the 1990s, until that team was transferred to Intel.

The point is that everybody in the industry knew the economics involved and it was a given that most proprietary architectures were going to being unable to be developed further. So under that lens, Itanium made some sort of sense as a path to a 64bit architecture where somebody else (intel) could eat most of the development costs, while giving the platform a collective economy of scale.

Except Itanium made no sense whatsoever economically and technically. This was known in some technical circles back when the vast majority of analysts were insisting that it could deliver what was claimed at a lower cost. Itanium merely required more complex and expensive compiler development while making barely any reductions in design cost. Itanium was as "hard" to design for as any non-VLIW/EPIC architecture. They ran into the same logic and circuit challenges as everyone else. The first Itaniums used plenty of the same expensive full-custom dynamic logic design as x86 (these had different logic styles though) and AMD (I believe the K8 et al. used dynamic logic; I could be wrong here).

Nowadays, we're starting to see similar dynamics. With AMD and Intel having to compete against ARM cores that are starting to be more performant while accessing larger economies of scale (and thus being able to tap more development investment)

From what I've seen, it's hard to compare the cost of AMD and Intel processors with ARM cores because most ARM cores are delivered as RTL, not macros. ARM licensees will do their own thing with the lower-level implementation/realization. That's not what AMD and Intel does. There will be lots of redundancy in R&D expenditure for ARM: ARM designs the architecture, organization, RTL, and maybe the physical design. Licencees will realize an ARM core from the RTL, or they might base their physical design on ARM's and make extensive modifcations themselves.