Intel has for a long time just had an extra step before decoders that finds the instruction boundaries. I’m not sure how complicated that problem actually is. Think about it, you are essentially reading a dozen or so bits and inferring instruction length from that, how many of your billions of transistors do you actually need for that? Afaik gracemont instruction cache stores also the instruction lengths so you don’t need to do that multiple times for cached code. I guess variable length makes the decoders a bit more complex though because they need to support handling varying input format.

Also, Intel’s clustered decoding in gracemont apparently can handle decoding a linear instruction stream with full width. It’s not just for branches. Technically it should improve performance around branches compared to non clustered decoder while performing similarly in linear code. In the upcoming skymont they will also be able to handle most microcoded instructions within cluster without blocking the other clusters like before.

It will be interesting to see if they are going to adopt this new decoding strategy for P-cores at some point. P-cores now rely on uops caching which the E-cores don’t seem to need.