Box64 and RISC-V in 2024 - What It Takes to Run The Witcher 3 on RiSC-V
Posted by takinaboutnuthin@reddit | hardware | View on Reddit | 20 comments
Posted by takinaboutnuthin@reddit | hardware | View on Reddit | 20 comments
sheokand@reddit
RISC-V is improving faster than ARM. Only if we can get some high-end desktop/laptop platform. this the best I could find, DC-ROMA RISC-V LAPTOP II - DeepComputing.
3G6A5W338E@reddit
Same SoC but much cheaper, on BPi-F3 (sbc) and MILK-V Jupiter (mini-itx).
sheokand@reddit
thanks
the_dude_that_faps@reddit
Obviously it is. RISC-V isn't on the bleeding edge of CPU design. We saw this with Apple during their lead up to Apple silicon and catching up to x86 dominance. Now performance upgrades are much more subdued.
Another way to look at it is that RISC V is picking the low hanging fruit from the metaphorical CPU design tree where as ARM has to get a ladder to pick one because the fruits closest to the base ran out.
dawnguard2021@reddit
Eventually we will. There are strong funding behind riscv to get it on par with arm/x86 asap.
Optifnolinalgebdirec@reddit
Who?
YumiYumiYumi@reddit
Except it kinda does, given the RISC philosophy of a minimal instruction set. RISC-V generally follows this, if you consider the number of instructions it provides, compared with its competitor ISAs.
jaaval@reddit
Talking about number of instructions can get a bit convoluted very quickly. Base RISC-V has like 50 instructions. It doesn't even include instruction for integer multiplication. To get better performance you need more specialized instructions. Which is why there is a large number of extensions to the base RISC-V.
All instructions in any instruction set were added to improve performance in some operation, you don't really need more than a dozen or so to have a fully functional computer but it makes no sense to do such a computer today.
YumiYumiYumi@reddit
Which each add a relatively small number of instructions. If you consider RVA22, you'll find it has significantly fewer instructions than x86/ARM.
jaaval@reddit
Yes, because few people have used it and had a reason to add new instructions. Those who use it now often add their own extra instructions for their specific application.
RVA22 seems to be just scalar integer and fp plus some control instructions. The number of instructions grows pretty fast when you start adding extensions. You are already way over 100 instructions with just adding the floating point scalar operations. And that doesn't yet have vectors or anything specialized. The vector extension alone is like 200 extra instructions.
Of course that isn't anywhere near the 1000-2000 (depending on what you count) instructions that are in x86-64 or ARM but it's getting there. Add some crypto acceleration etc. The number of instructions is fairly meaningless measure. Instructions are added as needed. Some fall out of use and if there are complex instructions that are not used they can be microcoded away from bothering chip design.
YumiYumiYumi@reddit
Yes, if you're building highly custom processors.
For general purpose cores, developers will only use standardised instructions. Just ask AMD how well 3DNow went for them.
What's "needed" is subjective though. RISC-V generally follows the philosophy of being conservative with adding new instructions. The number of instructions is used here as an indicator of this philosophy.
the_dude_that_faps@reddit
This is such a weird statement to make. Intel's MMX was a contemporary that was substantially more successful and both were eventually replaced by SSE. AMD didn't get adoption because they didn't command the market presence Intel had.
You could've said FMA3 and the same would've been true since that was replaced with both AVX and AVX2 both of which have seen massive adoption.
Software developers make use of instruction extensions all the time and don't stick to "standard" like you seem to imply. Just crypto extensions for crypto acceleration are an obvious one, just like vector math using SIMD instructions.
YumiYumiYumi@reddit
WTF? AVX/2 doesn't replace FMA3 and all modern x86 chips fully support FMA3.
AES-NI is also fully supported on all modern x86 chips. And like FMA3, will likely continue to be supported into the future.
3DNow was mentioned as an example of something AMD tried get adopted, but never did, and they dropped support for it due to lack of usage. The same will likely apply to vendor specific extensions - unless the vendor can get enough developers to use it, it'll end up being dead weight.
jaaval@reddit
Which by far the most risc-v use now is.
Are they? There seems to be dozens of extension development projects going on.
YumiYumiYumi@reddit
Yes, but when talking about application processors, i.e. ones that Box64 will be targeting, custom extensions aren't particularly relevant.
I can only speak of existing extensions, not new ones since we don't know what will be finalised. And for existing extensions, they are conservative.
the_dude_that_faps@reddit
This is such an oversimplification I'm tired at this whenever people point it out. Arm is "RISC" yet in armv8, once you count extensions, vector instructions, etc, it's close to 1000 instructions.
This distinction has lost its meaning for a long time. It's not even reduced complexity because there are quite a few complex instructions in the ARM ISA.
RISC V is nascent and there are already dozens of extensions to the base profile.
RISC at this point is more about a design philosophy than anything else because at the core, pretty much all modern CPUs decode instructions into micro ops and that's what actually gets executed.
YumiYumiYumi@reddit
Which ultimately means very little. You'll find that people attribute all sorts of things as "RISC", which makes it somewhat of a meaningless term.
RISC-V, on the other hand, follows more of an 80's definition of RISC, in being conservative with the number of instructions it supports.
Yes, there's many extensions, but even with those, the instruction set is still relatively small.
the_dude_that_faps@reddit
"Relatively small", so far the base spec doesn't even support integer multiplication. Which is fine, but isn't going to fly on a high performance design. Let me know how many actual instructions a high performance design that is competitive with arm or x86's best has when that eventually happens.
Don't get me wrong, I'm all for RISC V and anything that allows easier competitor entry than either of the current dominant architectures. But RISC V has a long way to go to be able to compete in performance.
YumiYumiYumi@reddit
I'm also not particularly convinced with the "RISC philosophy" (as in, having few instructions) being ideal for high performance designs, but it's the route RISC-V has decided to take.
GetsDeviled@reddit
This is cool!